Abstract: A power amplifier for a radio frequency transceiver including a driver, a disable circuit, and a bias circuit. The driver includes a source node for receiving a drive voltage when enabled and includes an output node that is susceptible to strong blocker signals when disabled. The bias circuit includes first and second bias nodes for driving the voltage level of the source and output nodes, respectively, to suitable bias voltage levels to minimize impact of blocker signals. The disable circuit includes switch circuits to couple the driver to the bias circuit in the disable mode. The bias circuit may include at least one voltage source. The bias circuit may be coupled to a supply voltage and may include a voltage divider coupled between the source and output nodes. The bias circuit may include a source-follower circuit to isolate the bias voltages from variations of the supply voltage.

Abstract: In one embodiment, an apparatus includes: a digital baseband circuit to receive a digital baseband signal and output a first digital baseband signal and a second digital baseband signal, the second digital baseband signal comprising a scaled version of the first digital baseband signal; a first transmitter signal path coupled to the digital baseband circuit to process the first digital baseband signal and output a first radio frequency (RF) signal; a second transmitter signal path coupled to the digital baseband circuit to process the second digital baseband signal and output a second RF signal; a first power amplifier coupled to the first transmitter signal path to amplify the first RF signal and output an amplified first RF signal; and a second power amplifier coupled to the second transmitter signal path to amplify the second RF signal and output an amplified second RF signal.

Abstract: In one form, a software system includes a first non-transitory computer readable medium storing a source code program, a second computer readable medium, and a compiler. The first non-transitory computer readable medium includes a first function having a return type greater than a native width of a target processor, and a second function that calls the first function and that conditionally branches based on comparing a returned value from the first function to an expected value, wherein the expected value has first and second portions that are not equal to zero and are not equal to each other. The compiler converts the source code program in the first non-transitory computer readable medium into a machine language program for storage in the second computer readable medium. The compiler optimizes the source code program by selectively combining a set of redundant machine language instructions into a smaller set of machine language instructions.

Abstract: A communications processor is operative in a plurality of modes including at least a high performance mode, a power savings mode with lower computational capability, and a shutdown mode with a wakeup capability. A memory for the communications processor has a high speed segment and a low speed segment, the high speed segment and low speed segment respectively on a high speed data bus and a low speed data bus, the high speed data bus and low speed data bus coupled by a bidirectional bridge.

Abstract: A system and method of minimizing interference and retries in an environment where two or more network protocols utilize the same frequency spectrum is disclosed. A lower-power network controller is co-located with a WIFI controller. The lower-power network controller listens for a signature that may indicate the presence of a low power protocol packet, such as BLE or Zigbee. The lower-power controller checks for a waveform that is representative of a Zigbee packet prior to generating a request signal to the WIFI controller. This maximizes the likelihood that no WIFI traffic will occur while the incoming packet is being received.

Abstract: An apparatus includes a power management circuit to receive an input voltage and to generate and provide a first output voltage to an energy storage device. The power management circuit further generates and provides a second output voltage to a load. The first output voltage is greater than the input voltage, and the second output voltage is smaller than the first output voltage. The apparatus further includes a monitor circuit to monitor the first output voltage and to provide a signal to the load to indicate when the load may perform an operation.

Abstract: An apparatus includes a radio frequency (RF) receiver. The RF receiver includes a timing correlator and frequency offset estimator. The timing correlator and frequency offset estimator: (a) extracts timing from a set of samples derived from an RF signal, and (b) determines a frequency offset estimate from the set of samples.

Abstract: A system and method for detecting and receiving Z-Wave Beams that are transmitted over a plurality of channels is disclosed. The system includes a radio circuit, which includes a Digital Signal Arrival (DSA) circuit and a read channel. The DSA circuit is able to detect the presence of a valid signal on a particular channel, based on received signal power, detected frequency deviation, the magnitude of phase spikes and/or other characteristics. The read channel is able to decode incoming packets. Software is used to control the DSA circuit and the read channel so that, during each wake up period, the FLiRS device monitors all available channels to determine if a Z-Wave Beam is present. If a Z-Wave Beam is detected, the read channel receives the Z-Wave Beam. Otherwise, the FLiRS device returns to sleep mode.

Abstract: A system and method for determining a direction of arrival of an incoming signal is disclosed. The present system utilizes a plurality of pseudo-spectrums to create a more accurate result matrix. The pseudo-spectrums are one or two dimensional arrays, where peaks in the arrays are indicative of the angle of arrival. A result matrix is generated by performing a mathematical operation of corresponding elements in each pseudo-spectrum. This mathematical operation may be addition or multiplication. The result matrix provides a more accurate indication of the angle of arrival than can otherwise by achieved. In some embodiments, a measure of quality may also be calculated for the result matrix.

Abstract: An integrated circuit includes a first plurality of circuits receiving a first internal power supply voltage, a first regulator receiving an external power supply voltage and supplying the first internal power supply voltage at a first rated power in response to the external power supply voltage when the integrated circuit is in an active mode, a second regulator receiving the external power supply voltage for supplying the first internal power supply voltage at a second rated power less than said first rated power in response to the external power supply voltage when the integrated circuit is in a low power mode, and a controller controlling a transition of the integrated circuit between the active mode and the low power mode. The controller activates all of the first plurality of circuits in the active mode, but only a subset of them while keeping remaining ones inactive in the low power mode.

Abstract: A data producer stores input data in a buffer in response to a slow clock signal and provides read data from the buffer in response to a read pointer signal. A data movement circuit reads the input data from the buffer using the read pointer signal and provides an update read pointer signal in response to reading the input data. The data movement circuit operates in response to a fast clock signal, and includes a metastable-free synchronizer circuit having inputs for receiving the update read pointer signal, the slow clock signal, and the read pointer signal, and an output for providing a synchronized read pointer signal equal to the read pointer signal except between a change in the read pointer signal while the slow clock signal is active until an inactivation of the slow clock signal. The buffer provides the read data in response to the synchronized read pointer signal.

Abstract: In one aspect, an apparatus includes: a buffer to store orthogonal frequency division multiplexing (OFDM) samples of one or more OFDM symbols; a fast Fourier transform (FFT) engine coupled to the buffer, the FFT engine to receive the one or more OFDM samples from the buffer and convert each of the one or more OFDM samples into a plurality of frequency domain sub-carriers; and a timing control circuit coupled to the buffer. The timing control circuit may control timing based at least in part on a difference between a first correlation sum for a first portion of a cyclic prefix of a first one of the one or more OFDM symbols and a second correlation sum for a second portion of the cyclic prefix.

Abstract: An IoT device has a public device identifier and a private device identifier, where the public device identifier is publicly available and the private device identifier is secret but kept in a secure device database as a correspondence. A registration request is sent from the IoT device to an association server in communication with the device database having an association between IoT public identifier and a corresponding IoT private identifier. The association server which receives the registration request responds with a registration acknowledgement containing, in encrypted form, the private device identifier of the original request and, optionally, the public device identifier associated with the registration request. The requesting IoT device receives the association acknowledgement, decrypts the private device identifier, compares it to its own device identifier, and if they match, sends one or more association requests.

Abstract: A data synchronizer including an input stage, a driver stage, and a keeper stage. The input stage latches input data to a data node in response to a first clock signal transition. The driver stage has an input coupled to the data node and has an output coupled to a gain node. The keeper stage latches data asserted on the gain node back to the input stage to maintain data on the data node in response to a second transition of the clock signal. The driver stage has an increased drive strength and a reduced loading capacitance to increase the gain-bandwidth product of the latch loop to reduce metastability. A flip-flop may be configured with input and output latches each including driver stages having increased drive strength and reduced loading capacitance to increase the gain-bandwidth product of each of the latch loops to reduce metastability.

Abstract: Systems and methods are provided that may be implemented to use resource filtering to provide multiple different device personalities and/or multiple different resources from a radio frequency (RF)-enabled wireless device or apparatus to one or more other connecting RF-enabled wireless devices across one or more wireless connections. In one example, each different given resource of a wireless device may be associated with at least one filter which may be used by the device to determine which connection/s the given resource may be provided, and a given resource may only be provided to a given connecting device only if the given resource passes the filter.

Abstract: Systems and methods are provided to simultaneously determine both angle of arrival (AoA) and angle of departure (AoD) of a signal transmitted between two or more radio frequency (RF)-enabled wireless devices (e.g., such as BLE modules). The disclosed systems and methods may be so implemented in one embodiment to determine AoD even in the case where the transmitting wireless device is at the same time operating in a departure (or AoD) transmitting mode by transmitting a RF signal from multiple antenna elements of at least one switched antenna array using a given switching pattern or sequence implemented by an array switch.

Abstract: A transmit/receive signal processor for Wireless Local Area Network (WLAN) and Bluetooth has selectable signal processing elements for mixers, Intermediate Frequency (IF) filters, transmit power amplifiers, and clock sources which are suitable for either Bluetooth or WLAN signal processing. The operating mode of the signal processor is selected to be one of Wireless High Performance, Wireless Low Power, Bluetooth High Performance or Bluetooth Low power, and the signal processing modules are selected to provide performance or power requirements using selected modules.

Abstract: A communications system has a low power connectivity processor and a high performance applications processor. The low power connectivity processor is coupled to a low power front end for wireless packets and the high performance applications processor is coupled to a high performance front end. A power controller is coupled to the low power front end and enables the applications processor and high performance front end when wireless packets which require greater processing capacity are received, and removes power from the applications processor and high performance front end at other times.

Abstract: A communications processor is operative in a plurality of modes including at least a high performance mode, a power savings mode with lower computational capability, and a shutdown mode with a wakeup capability. A memory for the communications processor has a high speed segment and a low speed segment, the high speed segment and low speed segment respectively on a high speed data bus and a low speed data bus, the high speed data bus and low speed data bus coupled by a bidirectional bridge.

Abstract: The resolution of a time to digital converter (TDC) is improved by using a gain stage at the input of the fine TDC. A delay line receives a pulse corresponding to the time information and recirculates the pulse in the delay line by coupling an output of the delay line to an input of the delay line. An integrating fine TDC receives a number of pulses from the delay line corresponding to the desired gain.