Abstract: A method includes receiving a differential voltage signal at first and second inputs of a comparator and selectively providing the differential voltage signal to one of a first conversion path and a second conversion path of the comparator during a conversion phase to determine a digital value corresponding to the differential voltage signal. The first and second conversion paths including first and second pluralities of gain stages, respectively. The method further includes coupling the selected one of the first conversion path and the second conversion path to an output to provide the digital value.

Abstract: A circuit includes a temperature sensor configured to determine a circuit temperature and includes an analog circuit including one or more controllable circuit elements. The analog circuit includes at least one adjustable parameter. The circuit further includes a controller coupled to the temperature sensor and configured to select a threshold temperature. The controller is configured to control the analog circuit in response to the circuit temperature to selectively adjust at least one adjustable parameter of the analog circuit when the temperature exceeds the selected threshold temperature.

Abstract: In one aspect, the present invention includes an apparatus having a digital signal processor (DSP), a controller coupled to the DSP to provide control signals to the DSP, and a one-time programmable (OTP) memory coupled to the DSP and the controller. The OTP memory may include multiple code portions including a first code block to control the DSP and a second code block to control the controller.

Abstract: A circuit includes a controller configured to determine a calibration state of a circuit, to determine an active mode state of the circuit, and to select a type of calibration operation based on the calibration state. The controller is configured to control timing of the selected type of calibration operation in response to determining the calibration state to correspond to a time when the circuit is not active.

Abstract: A micro electro mechanical system (MEMS) oscillator supplies an oscillator output signal having a first frequency that differs from a predetermined frequency of the output signal. An error determination circuit determines frequency error from the predetermined frequency based on initial frequency offset and/or temperature and provides the error information indicating a difference between the first frequency and the predetermined frequency. The error information is used by a receiving system in frequency translation logic that utilizes the oscillator output signal as a frequency reference.

Abstract: In one embodiment, an interface may include various mechanisms to handle incoming clock and data signals. More specifically, the interface includes a first multiplexer to receive a first data signal via a serial peripheral interface (SPI) bus coupled to a first pin and a second multiplexer to receive a first clock signal via the SPI bus coupled to a second pin of the first IC and a second clock signal via an inter-integrated circuit (I2C) bus coupled to a third pin. In addition, the interface may include a decoder to receive the second clock signal and a second data signal via the I2C bus coupled to a fourth pin.

Abstract: A method of communicating in an electronic system or apparatus is disclosed. The method includes using a processor to communicate with a peripheral. The method further includes using the peripheral to request a clock signal. The method also includes selectively control communication of the clock signal to the peripheral in response to the request.

Abstract: First order gradient errors are canceled with no current source splitting by placing consecutive current sources symmetrically around the center of the array. Consecutive elements that correspond to small input amplitudes (mid-scale codes) make a smaller spatial jump than those correspond to larger signal amplitudes. Both linear and second order gradients are reduced by splitting each current cell into two and placing sub-elements symmetrically with respect to the center of the array to address the linear gradient effect. To address second order gradients, current element placement follows a pattern such that consecutive element pairs are chosen with one of the pair being placed with respect to the zero error contour of the second order gradient so as to have a positive error and the second of the pair being placed so as to have a negative error resulting in reduced second order error accumulation.

Abstract: An apparatus includes an input/output (I/O) interface circuit that includes a memory and a controller. The memory stores a plurality of commands to regulate an input/output (I/O) interface. The commands indicate at least one I/O state of at least one I/O terminal of the I/O interface circuit and a time duration that is associated with the I/O state. The controller executes the commands to place the I/O interface in the the I/O state(s) in a predetermined sequence.

Abstract: A method of operating an amplifier circuit having a pre-charge phase and a sample/conversion phase includes, during a pre-charge phase, charging first and second capacitors to first and second bias voltages. The first capacitor is coupled to a first input of an amplifier circuit, which has a second input and an output. The second capacitor is coupled to the second input. During a sample/conversion phase, the first input of the amplifier circuit is coupled to an input signal through the first capacitor to level-shift the input signal according to the first bias voltage and the output of the amplifier is coupled to the second input through the second capacitor to level shift a feedback signal according to the second bias voltage.

Abstract: A circuit includes a comparator including a first input, a second input, and an output. The circuit further includes a plurality of capacitive sampling circuits configured to be selectively coupled to the first and second inputs. Each of the plurality of capacitive sampling circuits includes first and second capacitors, and includes first and second conversion switches configured to selectively couple the first and second capacitors to the first and second inputs, respectively. The first and second conversion switches of a selected one of the plurality of capacitive sampling circuits are closed to couple the selected one to the first and second inputs of the comparator during a conversion phase.

Abstract: An apparatus includes an integrated circuit. The integrated circuit includes a low-noise amplifier having a first complex input impedance. The integrated circuit includes a complex attenuator coupled to an input terminal of the integrated circuit. The complex attenuator has a second complex input impedance and a first complex output impedance. The apparatus may include a matching network coupled to the input terminal of the integrated circuit. The matching network is external to the integrated circuit. The matching network may have a first real input impedance and a second complex output impedance. The second complex output impedance is matched to the second complex input impedance.

Abstract: On-chip decoupling capacitors and methods for placing the same are disclosed in which designated spaces are created between the active circuits to insert designated capacitor cells. The designated capacitor cells may be placed in designated areas of the integrated circuit that are not simply spaces left empty by cell placement or frontier areas in or around the route, and the dimensions (e.g., height) of the designated capacitor cells may be selected to optimize (increase) capacitance efficiency. The capacitor cells may also be placed to target and reduce the interference between a digital core (aggressor) circuit and a victim analog circuit.

Abstract: A semiconductor wafer including a plurality of die fabricated therein in a defined pattern. They are separated from each other by a dicing area or street and at least a portion of adjacent die on the wafer include at least a conductive connection between given adjacent die that is electrically interfaced to circuitry disposed on the given adjacent die.

Abstract: A digital radio signal is processed by converting an analog signal to a digital signal, decimating the digital signal using a CIC filter and supplying the decimated digital signal directly to an asynchronous sample rate converter (ASRC). The decimated signal is resampled in the ASRC and the ASRC output is supplied directly to a droop compensation filter to compensate the output of the ASRC. By carefully choosing the response of the CIC filter and the resample rate of the ASRC, aliased artifacts in the pass band can be kept below a threshold magnitude without the need for a channelization filter.

Abstract: Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The receiver analog circuitry and the receiver digital circuitry are partitioned so that interference effects between the receiver analog circuitry and the receiver digital circuitry tend to be reduced.

Abstract: A receiver includes a phase click detector, a controller, and a comparator. The phase click detector detects phase clicks in an input signal, where a phase click corresponds to a change in phase of at least a first threshold. The controller is coupled to the phase click detector for calculating a number of phase clicks within one or more time periods. The comparator compares the number of phase clicks within the one or more time periods, and provides an arrival signal if the number of phase clicks is less than a second threshold.

Abstract: A system for reducing noise when detecting the capacitance value of a capacitor in a touch display that operates in a potentially noisy environment. A capacitance sensor is provided for determining the size of the capacitor in the touch screen display and includes a charging circuit that charges the capacitor and a discharge circuit that resets the charge of the capacitor to substantially zero. A control circuit controls the capacitance sensor and the operation of the charge and discharge circuits in accordance with a predetermined charging/discharging algorithm to resolve the value of the capacitor and output such value in a sampling operation. The operation of the control circuit and the charging/discharging algorithm is subject to errors as a function of the noisy environment, which errors will be reflected in the output value. A noise reduction circuit is provided to modify the operation of the control circuit to reduce noise.

Abstract: A one-wire transmission protocol utilizes transition interval coding in which a value of a transmitted symbol is determined by comparing an interval length between the voltage transition associated with the transmitted symbol and a prior voltage transition on the communication link, to a threshold transition interval provided to the receiving device during the transmission sequence that includes the transmitted symbol. If the interval length of the symbol is below the transition interval threshold, the symbol is determined to be a first value and if the interval length of the symbol is above the transition interval threshold, the symbol is determined to be a second value. The transition interval threshold is provided in a start sequence that includes at least two transitions. The threshold transition interval width is based on one or more transition intervals determined during the start sequence.

Abstract: An apparatus includes a microcontroller unit (MCU). The MCU includes a buffer and an analog comparator that are coupled to an input of the MCU. The MCU is adapted to selectively determine a logic value of a digital signal applied to the input of the MCU from an output signal of the buffer or from an output signal of the analog comparator.