Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract: Various techniques for reducing power in a wireless network device are disclosed. In some embodiments, software routines within the device are modified to minimize the time during which the analog circuitry in a radio is powered. In some embodiments, the techniques make use of knowledge of implied delays associated with a particular network protocol. For example, in a CSMA network, there is a defined minimum period before the device can attempt to gain access to the media. The radio may be powered off during this defined period. In other embodiments, modifications to a protocol are disclosed which allow additional power savings.

Abstract: In one embodiment, an apparatus includes a first receiver path with a first digitizer to digitize an incoming signal obtained from a radio frequency signal including at least a first desired channel into samples, the first digitizer to operate at a first sampling frequency, a first sample rate converter coupled to an output of the first digitizer to receive the samples at the first sampling frequency and to output the samples at a fixed sampling frequency, and a first digital processor to receive and process the samples at the fixed sampling frequency. The apparatus may further include a controller to receive a frequency change indication and to dynamically control the first sample rate converter to accommodate a change in the first sampling frequency from a first rate to a second rate.

Abstract: Circuit configurations and related methods are disclosed that may be implemented to protect circuitry from adverse effects of transistor snapback that may occur during ESD events. The circuitry and methods may be implemented as part of distributed ESD rail clamping circuitry that includes ESD circuit elements that are coupled to power nodes or supply rails and not to signal nodes or signal pads of the circuitry in a manner that reduces parasitic loading on signal pads to reduce or substantially eliminate NMOS and/or PMOS transistor snapback occurrence, while at the same time providing rail-clamping capability during occurrence of ESD events.

Abstract: A radio frequency (RF) device is provided. The RF device includes an antenna interface, a receive circuit configured to extract data from incoming signals, a playback circuit configured to associate a predefined delay with the data, a transmit circuit configured to generate outgoing signals based on the data and the predefined delay, and a control circuit configured to calculate range based in part on the predefined delay and phase differences between incoming signals and outgoing signals.

Abstract: In some cases, it may be desirable to limit the number of routers in a mesh network. Various techniques to limit the number of routers, without affecting connectivity, are disclosed. In some embodiments, a node enables its router capability if there are less than a predetermined number of routers already in the network. In other embodiments, a node enables its routing capability only is it is necessary to resolve a connectivity issue or a biconnectivity issue. In some cases, a node, which previously enabled its router capability, may no longer be required to be a router. In some embodiments, this node, upon making this determination, disables its routing capability.

Abstract: A controller for a brushless direct current (BLDC) motor includes a pulse width modulator and a control circuit. The pulse width modulator provides a plurality of phase control signals to control corresponding ones of a plurality of phases of the BLDC motor. The control circuit controls the pulse width modulator to provide pulses to the plurality of phases to control a speed of the BLDC motor by causing the pulse width modulator to adjust widths of the pulses when a measured current in an active one of a corresponding phase exceeds a threshold in a startup mode. In one form, the controller is part of a BLDC motor system which also includes a plurality of phase drivers each having inputs for receiving respective ones of said plurality of phase control signals, and outputs adapted to couple to corresponding phases of the BLDC motor.

Abstract: A controller for a BLDC motor includes a pulse width modulator and a control circuit. The pulse width modulator provides at least one phase control signal for a corresponding phase of the BLDC motor with a pulse width determined by a duty cycle signal. The duty cycle adjustment circuit has an input for receiving the at least one phase control signal, and an output for providing a corresponding modified phase control signal by adjusting widths of pulses of the at least one phase control signal when an average current in said corresponding phase exceeds a threshold.

Abstract: A method includes estimating a temperature change to an integrated circuit, which is associated with a pending transmission from the integrated circuit.

Abstract: An apparatus includes a controller and a comparator. The controller generates pulse width modulation (PWM) signals to drive stator windings of a brushless direct current (BLDC) motor in a commutation sequence such that one of the stator windings at a given time is open; and generates a tracking signal synchronized to the PWM signals and indicative of times when a leakage current is present in the open stator winding. The comparator senses when a back electromotive force of the open stator winding has an associated zero crossing. The sensing by the comparator is selectively enabled and disabled by the tracking signal.

Abstract: A circuit includes a discriminator to store a threshold. The circuit further includes a comparator including a first input to receive a count, a second input to receive the threshold, and an output to provide an output signal representing a result of the comparison between the count and the threshold. The circuit also includes a controller to automatically adjust the threshold when the count exceeds a first threshold or falls below a second threshold.

Abstract: A metering circuit includes a comparator including a first input to receive an input signal, and including a second input and an output. The metering circuit further includes a reference source to provide a time-varying reference signal to the second input during a peak counting operation.

Abstract: In a particular embodiment, a method of producing a powered device detection signature includes rectifying a device detection input received from a powered network to produce a rectified detection input at a powered device. The method further includes applying the rectified detection input to a signature resistor and to a variable impedance circuit in parallel with the signature resistor to produce a device signature that is substantially constant over a power range associated with the device detection input.

Abstract: An apparatus for communicating using an isolation channel includes a transmitter circuit having a first terminal configured to communicate a first signal. The first signal oscillates in response to a data signal having a first signal level and is constant in response to the data signal having a second signal level. The transmitter circuit includes a second terminal configured to communicate that oscillates in response to the data signal having the second signal level and is constant in response to the data signal having the first signal level. The apparatus may include a receiver circuit configured to generate a recovered data signal having a first transition in a first direction between first and second levels based on an edge of a first received signal and having a second transition in a second direction between the first and second levels based on an edge of a second received signal.

Abstract: An LCD controller includes a charge pump for generating a charge voltage responsive to an external voltage and a clock signal. The controller further includes an oscillator for generating the clock signal responsive to an oscillator control signal. An LCD driver voltage circuit generates a plurality of LCD driver voltages for driving segments of an associated LCD display. A loop control circuit within the LCD controller monitors an LCD driver voltage from the LCD driver voltage circuit and generates the oscillator control signal responsive thereto to enable and disable the oscillator.

Abstract: Variable capacitive attenuation circuitry and associated methods are disclosed that may be implemented to employ a plurality of multi-purpose capacitors that may be selectably coupled together in different configurations to form a capacitive divider having different respective attenuation properties. In a particular embodiment, each of the capacitors of the disclosed capacitive attenuation circuitry may be selectably coupled to an RF reference as either a shunt capacitor or coupled in series between an RF signal input and an attenuated RF signal output as a series capacitor, thus forming a capacitive divider having selected attenuation properties. The disclosed variable capacitive attenuation circuitry may be advantageously utilized to attenuate an input RF signal and to provide a resulting attenuated RF output signal, for example, in the front end of RF receiver circuitry.

Abstract: Systems and methods are disclosed for shared AM/FM air loop antennas that may be advantageously implemented to provide a AM/FM receiver system with a single common air loop antenna for receiving both AM and FM channels, thus eliminating the need for additional materials and electronics associated with provision of a separate FM pigtail antenna and FM antenna jack for connection of same. The shared AM/FM air loop antennas may be connected to a radio device having antenna connections.

Abstract: An apparatus includes an integrated circuit (IC) adapted to be powered by a positive supply voltage. The IC includes a charge pump that is adapted to convert the positive supply voltage of the IC to a negative bias voltage. The IC further includes a bidirectional interface circuit. The bidirectional interface circuit includes an amplifier coupled to the negative bias voltage to accommodate a bidirectional input voltage of the IC. The bidirectional interface circuit further includes a comparator coupled to the negative bias voltage to accommodate the bidirectional input voltage of the IC.

Abstract: A relaxation oscillator circuit includes a comparator including a first input, a second input, a bias input, and an output. The first input is coupled to a charging node, and the second input is configured to receive a reference voltage. The relaxation oscillator circuit further includes a first bias circuit configured to provide a bias signal to the bias input of the first comparator when a first node voltage on the charging node exceeds a first reference.

Abstract: Various techniques for automatic amplitude control of an oscillator are described. An apparatus includes an oscillator circuit configured to generate an oscillating signal. The apparatus includes a feedback circuit configured to control a bias signal of the oscillator circuit to maintain a target peak amplitude of the oscillating signal based on a current-mode indicator of a peak amplitude of the oscillating signal and a reference current. The feedback loop includes a rectifier circuit configured to generate the current-mode indicator and a summing node configured to provide a bias control signal based on a difference between the current-mode indicator and the reference current. The feedback circuit may include a capacitor coupled to the summing node and configured to accumulate charge according to the difference. A magnitude of the current-mode indicator may be at least two orders of magnitude less than a magnitude of the current through an output node of the oscillator circuit.