Abstract: An apparatus includes a thermistor having a variable resistance with a first dependence on absolute temperature. The apparatus includes a reference resistor having a resistance with a second dependence on absolute temperature, the second dependence being less than or having opposite polarity to the first dependence. The reference resistor includes a switched-capacitor circuit. The apparatus includes a node coupled between the thermistor and the reference resistor. The node is configured to provide a signal indicative of absolute temperature based on the variable resistance and the reference resistance. The signal may be strain-invariant, proportional to a reference voltage, and indicative of a ratio of the variable resistance to the reference resistance. The apparatus may include a feedback circuit configured to maintain the node at a predetermined voltage level.

Abstract: An apparatus includes an integrated circuit. The integrated circuit includes a low-noise amplifier having a first complex input impedance. The integrated circuit includes a complex attenuator coupled to an input terminal of the integrated circuit. The complex attenuator has a second complex input impedance and a first complex output impedance. The apparatus may include a matching network coupled to the input terminal of the integrated circuit. The matching network is external to the integrated circuit. The matching network may have a first real input impedance and a second complex output impedance. The second complex output impedance is matched to the second complex input impedance.

Abstract: A system for communicating information includes one device that communicates information via a communication link. The system also includes a second device to communicate information via the communication link. The second device includes a receiver to receive information from the communication link. The second device also includes an oscillator that provides at least one timing signal to the receiver. The oscillator is disabled when the communication link is in an idle state. The oscillator is enabled when the communication link is in a non-idle state.

Abstract: An apparatus includes a detector to detect an idle state of a communication link that communicates bursts or packets of information. The apparatus also includes an oscillator having low-power and normal modes of operation. The oscillator makes a transition to the low-power mode during the idle state of the communication link. The oscillator leaves the low-power mode of operation and enters the normal mode of operation when the communication link is in a non-idle state.

Abstract: An apparatus includes a signal generator and a control circuit. The signal generator includes a control terminal and includes a current electrode coupled to a terminal that is configured to couple to a power line to receive direct current (DC) power from a power generator. The control circuit is coupled to the current electrode and the control terminal of the signal generator. The control circuit determines an impedance associated with the power generator and applies a control signal to the control terminal of the signal generator to produce an impedance adjustment signal on the current electrode for communication to the power generator through the power line in response determining the impedance.

Abstract: An analog signal is transported across an isolation channel using edge modulation/demodulation of a pulse width modulated (PWM) signal. An edge modulator is responsive to rising edges of the PWM signal to generate first pulses having a first predetermined pulse width and is responsive to receipt of falling edges of the PWM signal to generate second pulses having a second predetermined pulse width with the same polarity as the first pulses. On the opposite side of the isolation channel an edge demodulating circuit recreates the PWM signal using the first and second pulses. The rise and falling edges of the PWM signals can be distinguished based on the pulse width of the first and second pulses. A second order pulse width modulator may be used to generate the PWM signal.

Abstract: In one embodiment, an apparatus includes a first receiver path with a first digitizer to digitize an incoming signal obtained from a radio frequency signal including at least a first desired channel into samples, the first digitizer to operate at a first sampling frequency, a first sample rate converter coupled to an output of the first digitizer to receive the samples at the first sampling frequency and to output the samples at a fixed sampling frequency, and a first digital processor to receive and process the samples at the fixed sampling frequency. The apparatus may further include a controller to receive a frequency change indication and to dynamically control the first sample rate converter to accommodate a change in the first sampling frequency from a first rate to a second rate.

Abstract: In one form, a multi-chip module for a multi-mode receiver includes an MCM substrate and first and second demodulator die. The MCM substrate has first and second satellite input ports, first and second terrestrial/cable input ports, and first and second transport stream ports. The first demodulator die has a satellite port coupled to the first satellite input port of the MCM substrate, a terrestrial/cable port coupled to the first terrestrial/cable input port of the MCM substrate, and first and second transport stream ports coupled to the first and second transport stream ports of the MCM substrate. The second demodulator die has a satellite port coupled to the second satellite input port of the MCM substrate, a terrestrial/cable port coupled to the second terrestrial/cable input port of the MCM substrate, and first and second transport stream ports coupled to the first and second transport stream ports of the MCM substrate.

Abstract: In one embodiment, a receiver front end circuit can receive and process multiple radio frequency (RF) signals and output downconverted signals corresponding to these signals. In turn, multiple signal processors can be coupled to this front end. Specifically, a first signal processor can receive and process the downconverted signals to output a first signal obtained from content of a first RF signal, and a second signal processor can receive and process the downconverted signals to output a second signal obtained from content of a second RF signal. In addition, the apparatus may include a detection circuit coupled to the receiver front end circuit to detect presence of at least the second signal and enable the second signal processor responsive to the detected presence.

Abstract: In an embodiment, an apparatus includes a first tuner to receive a radio frequency (RF) signal from a first antenna and to process the RF signal to generate a first time-domain quadrature signal, a second tuner to receive the RF signal from a second antenna and to process the RF signal to generate a second time-domain quadrature signal, and a combiner circuit to receive the first and second time-domain quadrature signals.

Abstract: A first integrated circuit die receives input data from a plurality of input channels and combines the input data from the plurality of input channels into combined data. The first integrated circuit die transmits the combined data across an isolation communication channel. A second integrated circuit die that is coupled to the isolation communication channel decodes the transmitted combined data and supplies the decoded transmitted combined data to respective output channels corresponding to the input channels.

Abstract: Diode circuit layout topologies and methods are disclosed that exhibit reduced lateral parasitic bipolar characteristics at lateral parasitic bipolar circuit emitter edges during ESD or other voltage events as compared to conventional circuit layout topologies. The disclosed diode circuit layout topologies may be implemented to recess parasitic emitter ends relative to surrounding well ties, for example, to reduce or substantially eliminate parasitic bipolar action at lateral emitter edges of the circuitry during ESD events so as to provide higher current threshold for device failure, allowing for smaller device area and/or improved ESD robustness for a given circuit device.

Abstract: Data flow control in a television receiver controls the output of the frequency deinterleaver (FDI) and the time deinterleaver (TDI) to prioritize processing control information having transmission parameters needed for processing data, thereby facilitating use of one FEC decoder.

Abstract: A motor control apparatus to control a motor external to the motor control apparatus includes a microcontroller unit (MCU). The MCU includes mixed signal motor control circuitry adapted to perform back electromotive force (EMF) motor control in a first mode of operation. The mixed signal motor control circuitry is further adapted to perform field oriented control (FOC) in a second mode of operation.

Abstract: An apparatus includes a splitter to receive a radio frequency (RF) signal and to provide the RF signal to multiple channels of a tuner. Each channel may include an amplifier to amplify the RF signal, a mixer to downconvert the amplified RF signal to a second frequency signal using a local oscillator (LO) signal, where each of the channels is configured to receive a different LO signal, a filter to filter the downconverted second frequency signal, and a digitizer to digitize the downconverted second frequency signal. A clock generation circuit has multiple interpolative dividers and a frequency synthesizer to generate a reference clock signal. Each of the interpolative dividers is configured to receive the reference clock signal, generate a corresponding LO signal, and provide the corresponding LO signal to the mixer of at least one of the channels.

Abstract: A phase-locked loop (PLL) is provided. The PLL may include a local oscillator configured to generate an output signal, a feedback divider configured to generate a feedback signal in response to the output signal, a phase detector configured to operate the local oscillator based on a comparison between a reference signal and the feedback signal, and a reset controller in communication with each of the phase detector and the feedback divider. The reset controller may be configured to hold each of the phase detector and the frequency divider in reset, and enable each of the phase detector and the frequency divider such that at least the feedback signal is in substantial synchronization with the reference signal.

Abstract: A system and method of calibrating a phase-locked loop (PLL) having at least a phase detector, a frequency divider and a local oscillator are provided. The disclosed example includes generating a lock window signal based on a feedback signal generated by the frequency divider where the lock window signal may form an active lock window relative to each significant edge of the feedback signal, generating a sampled window signal based on samples of the lock window signal at each significant edge of a reference signal, and estimating a phase offset between the reference signal and the feedback signal based on a number of consecutive samples of the sampled window signal that are active.

Abstract: In an embodiment, a method includes: during a first portion of a cycle of a clock signal generated by an oscillator, pre-charging a first capacitor of a first switched capacitor stage until a first comparator determines that a first node voltage of the first switched capacitor stage is greater than a first reference voltage at a first reference voltage node; applying a second reference voltage to the first reference voltage node; and responsive to a first edge of the clock signal, charging the first capacitor until the first comparator determines that the first node voltage is greater than the second reference voltage at the first reference voltage node.

Abstract: Current flowing through an inductor on a primary side of a voltage converter is sensed and compared to a threshold peak current value to determine when to end an ON portion of the voltage converter. The secondary side of the voltage converter supplies an indication of output voltage for use in determining the threshold peak current value. On start-up the primary side detects when the indication of output voltage is supplied by the secondary side across on isolation channel. Prior to detecting the indicating is being supplied, the primary side uses an increasing threshold peak current as the threshold peak current value. After detection that the indication of output voltage is being provided by the secondary side, the threshold peak current value is based on the indication of the output voltage.

Abstract: First order gradient errors are canceled with no current source splitting by placing consecutive current sources symmetrically around the center of the array. Consecutive elements that correspond to small input amplitudes (mid-scale codes) make a smaller spatial jump than those correspond to larger signal amplitudes. Both linear and second order gradients are reduced by splitting each current cell into two and placing sub-elements symmetrically with respect to the center of the array to address the linear gradient effect. To address second order gradients, current element placement follows a pattern such that consecutive element pairs are chosen with one of the pair being placed with respect to the zero error contour of the second order gradient so as to have a positive error and the second of the pair being placed so as to have a negative error resulting in reduced second order error accumulation.