Abstract: A receiver includes a first amplifier having an input for receiving an RF signal, and an output for providing an amplified RF signal, a switch section that selectively switches the amplified RF signal onto a selected one of a plurality of nodes, and a filter section comprising a plurality of filters coupled to respective ones of the plurality of nodes. A first filter of the plurality of filters comprises a first variable capacitor coupled in parallel with an inductance leg between a corresponding one of the plurality of nodes and a power supply voltage terminal. The first variable capacitor has a capacitance that varies in response to a tuning signal. The inductance leg includes a first inductor in series with an effective resistance, wherein the effective resistance has a value related to an upper cutoff frequency to be tuned by the first filter.

Abstract: A circuit includes a power supply terminal and a clock parsing circuit configured to produce multiple clock signals having a common clock period and different phases. The circuit further includes a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal. Each digital circuit includes an input to receive data and logic to process the data. Each digital circuit is responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the regulated power supply terminal to process the data to produce a data output. Additionally, the circuit includes an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits.

Abstract: A successive approximation register (SAR) ADC includes an SAR comparator circuit including first and second inputs, a control input, and first and second outputs. The SAR comparator circuit further includes a plurality of capacitors coupled to the first and second inputs and includes a plurality of switches configured to couple the plurality of capacitors to one of a first voltage and a second voltage. The SAR ADC further includes a calibration circuit coupled to the first and second outputs and to the control input of the SAR comparator. The calibration circuit is configured to control the plurality of switches to selectively couple the plurality of capacitors to one of the first and second voltages to provide a calibration signal to the SAR comparator circuit. The calibration circuit is configured to calibrate the SAR comparator based on corresponding output signals at the first and second outputs.

Abstract: Radio frequency (RF) receivers having whitened digital clocks and related methods are disclosed. Disclosed embodiments generate whitened clocks having random variations that are used to operate digital processing blocks so that interference created by the whitened clocks is seen as white noise within the received RF signal spectrum. RF input signals are received by RF front-ends (RFFEs) that output analog signals associated with channels within the RF input signals. These analog signals are converted to digital information and processed by digital receive path circuitry that outputs digital data associated with the channel. The digital receive path circuitry includes a whitened clock generator that generates a whitened clock having random variations and which a digital processing block that operates based upon the whitened clock. Further, the RFFE and the digital receive path circuitry are located within a single integrated circuit.

Abstract: An integrated circuit includes a pulse generator to provide an excitation pulse to an output terminal and a comparator to receive a signal in response to the excitation pulse and for comparing the signal to a threshold to produce a comparator output signal corresponding to oscillations in the signal. The integrated circuit further includes a counter to count pulses in the comparator output signal and a discriminator circuit to compare a count value of the counter to a damping threshold and for providing an output signal having a first value when the count value is equal to or exceeds the damping threshold and otherwise having a second value.

Abstract: A method includes receiving a differential voltage signal at first and second inputs of a comparator and selectively providing the differential voltage signal to one of a first conversion path and a second conversion path of the comparator during a conversion phase to determine a digital value corresponding to the differential voltage signal. The first and second conversion paths including first and second pluralities of gain stages, respectively. The method further includes coupling the selected one of the first conversion path and the second conversion path to an output to provide the digital value.

Abstract: An integrated circuit includes a first port for conducting a first plurality of signals, a second port for conducting a second plurality of signals, a data path coupled between the first port and the second port, a controller, and a processor having an input and an output. In a first mode, the controller causes the data path to conduct at least one signal received on the first port to the second port. In a second mode, the controller controls the processor to output signals to the second port.

Abstract: Techniques are disclosed relating to generating compatible clock signals. In one embodiment, an apparatus is configured to receive an input clock signal and a reference clock signal. In this embodiment, the apparatus includes a rate estimation unit and a phase-locked loop (PLL) unit. In this embodiment, the PLL unit is configured to generate, using a control signal from the rate estimation unit and the input clock signal, a PLL output clock signal. In this embodiment, the rate estimation unit is configured to adjust the control signal such that the PLL output clock signal and the reference clock signal are compatible. In this embodiment, the rate estimation unit is configured to adjust the control signal based on the reference clock signal and a comparison clock signal generated by the apparatus based on the PLL output clock signal.

Abstract: An image rejection (IR) circuit is configured to receive a complex signal from a radio frequency (RF) mixer, where the complex signal includes an in-phase signal portion and a quadrature signal portion. This IR circuit may include: an in-phase path to remove first mismatch information from the in-phase signal portion and associated with at least one in-phase multi-tap filter; a quadrature path to remove second mismatch information from the quadrature signal portion and associated with at least one quadrature multi-tap filter; and a correlation unit to independently update each of the multiple taps of the in-phase multi-tap filter and the quadrature multi-tap filter according to a priority scheme.

Abstract: An integrated circuit includes a tuner, a digital television (DTV) demodulator, an analog television (ATV) demodulator, and a controller. The tuner includes an input for receiving a radio frequency (RF) signal including at least one of an analog television signal and digital television signal, and including a first output terminal and a second output terminal. The DTV demodulator includes a DTV input coupled to the first output terminal of the tuner and includes a DTV output terminal. The ATV demodulator includes an ATV input coupled to the second output terminal of the tuner and includes an ATV output terminal. The controller is coupled to the tuner, the DTV demodulator, and the ATV demodulator to configure the tuner and at least one of the DTV demodulator and the ATV demodulator for receiving television content in a selected television format.

Abstract: A receiver includes first, second, and third signal processors and a controller. The first signal processor provides a first signal in response to detecting a first attribute of a received signal. The second signal processor provides a second signal in response to detecting a second attribute of the received signal. The third signal processor provides a third signal in response to detecting a third attribute of the received signal and provides packet data. The controller enables the first signal processor in response to a receive enable signal, controls the third signal processor to provide the packet data in response to receiving the first signal and the third signal, and initializes the first signal processor and the third signal processor in response to receiving the first signal and the second signal.

Abstract: An energy profiling apparatus for profiling power consumption characteristics of code being executed at an integrated circuit being powered by a power source and having a measurement module, a data processing module and a display module is disclosed. The energy profiling apparatus comprises first, second and third interfaces as well as a profile module. The first interface is configured to receive a first data set from the measurement module. The second interface is configured to receive a second data set from the data processing module. The third interface is configured to transmit a third data set to the display module. The profile module is configured to generate an energy profile of the code executed at the data processing module based on a correlation between the first data set and the second data set. Furthermore, the profile module is configured to transmit the energy profile as part of the third data set to the display module.

Abstract: Spur cancellation systems and related methods are disclosed for radio frequency (RF) receivers and other implementations. Disclosed embodiments effectively remove spurs caused by digital clock signals or other spur sources by determining which spurs will fall within a channel selected to be tuned, utilizing a spur cancellation module to generate a cancellation signal, and subtracting this cancellation signal from the digital information. The cancellation signal can be initially generated with a known frequency and estimated values for unknown spur parameters, such as amplitude and phase. Digital feedback signals are then used to adjust the spur parameters. If the spur frequency is not known precisely, digital feedback signals can also be used to adjust the frequency of the cancellation signal. Where multiple receive paths are provided within a multi-receiver system, multiple spur cancellation modules can be used to remove spurs generated by digital clocks within each of the receive paths.

Abstract: Radio frequency (RF) receivers having whitened digital clocks and related methods are disclosed. Disclosed embodiments generate whitened clocks having random variations that are used to operate digital processing blocks so that interference created by the whitened clocks is seen as white noise within the received RF signal spectrum. RF input signals are received by RF front-ends (RFFEs) that output analog signals associated with channels within the RF input signals. These analog signals are converted to digital information and processed by digital receive path circuitry that outputs digital data associated with the channel. The digital receive path circuitry includes a whitened clock generator that generates a whitened clock having random variations and which a digital processing block that operates based upon the whitened clock. Further, the RFFE and the digital receive path circuitry are located within a single integrated circuit.

Abstract: A technique for forming an encapsulated microelectromechanical system (MEMS) device includes forming an integrated circuit using a substrate, forming a barrier using the substrate, and forming a MEMS device using the substrate. The method includes encapsulating the MEMS device in a cavity. The barrier is disposed between the integrated circuit and the cavity and inhibits the integrated circuit from outgassing into the cavity. The barrier may be substantially impermeable to gas migration from the integrated circuit.

Abstract: Pop/clock noise reduction circuitry is disclosed for audio output circuitry. After audio output circuitry is enabled, reference voltage generator circuitry is then enabled to produce a reference voltage that ramps from a first voltage level to a second voltage level at a smooth rate. The ramping reference voltage is applied to the input of the audio output circuitry to reduce or prevent pop/click noise for the audio output circuitry. Further, negative offset control circuitry can also be used to provide a negative offset input to the audio output circuitry to remove initial step-up voltage levels that may exist at operational power-up for the audio output circuitry. Still further, current control circuitry can also be used that limits the available current flowing to the output node for the audio output circuitry, thereby further reducing and/or preventing potential pop/click noise in the audio output signals.

Abstract: A radio frequency (RF) receiver front end includes an RF attenuator for receiving an RF input signal and a low noise amplifier (LNA). In one form, the LNA provides a differential output signal and includes a first polarity amplifier and a plurality of second polarity amplifiers. The first polarity amplifier has an input terminal coupled to the output of the RF attenuator, an output terminal for providing a first component of the differential RF output signal, and has a first input impedance. Each of the plurality of second polarity amplifiers has an input terminal coupled to the output of said RF attenuator, and an output terminal. The output terminals of said plurality of second polarity amplifiers are coupled together and form a second component of the differential RF output signal. Each of the plurality of second polarity amplifiers has a second input impedance higher than the first input impedance.

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract: A method of handling a collision event between a first and second transmission includes detecting a collision event between the first and second transmissions while processing the first transmission at a receiver. The method further includes halting decoding of the first transmission in response to detecting the collision, adjusting receive parameters to receive the second transmission, and detecting a preamble portion of the second transmission using the adjusted receive parameters.

Abstract: A method of operating a system including a MEMS device of an integrated circuit die includes generating an indicator of a device parameter of the MEMS device in a first mode of operating the system using a monitor structure formed using a MEMS structural layer of the integrated circuit die. The method includes generating, using a CMOS device of the integrated circuit die, a signal indicative of the device parameter and based on the indicator. The device parameter may be a geometric dimension of the MEMS device. The method may include, in a second mode of operating the system, compensating for a difference between a value of the signal and a target value of the signal. The method may include re-generating the indicator after exposing the MEMS device to stress and generating a second signal indicating a change in the device parameter.