Abstract: A flash memory controller includes a controller circuit and a scheduler circuit. The controller circuit receives a multi-plane read command signal sent from a host device to respectively read data of storage pages, corresponding to the carried address information, on multiple memory planes within a flash memory. The controller circuit stores the first read commands in the first pending list and stores the second read commands in the second pending list. The scheduler circuit reorders the read commands stored in the first and second pending lists to make first data output time intervals be staggered and not overlap with second data output time intervals.

Abstract: A memory controller is provided, which includes a processor having a plurality of processing cores, and a lookup acceleration circuit. The lookup acceleration circuit includes a message processing circuit and a logical-to-physical mapping table lookup circuit. The message processing circuit receives request messages from the processing cores using request queues, and puts an incoming request message to a collision pending queue in response to detection of a collision between a first logical address range within the incoming request message and second logical address ranges within message contexts corresponding to active request messages. The logical-to-physical mapping table lookup circuit looks up a logical-physical mapping table in a volatile memory to convert the second logical address ranges into first physical addresses. The message processing circuit performs memory access operations corresponding to the active request messages on the volatile memory using the first physical addresses.

Abstract: The present invention provides a control method for a flash memory controller and an associated device, wherein the flash memory controller is coupled between a host device and a flash memory module. By setting a first bandwidth for communicating with the host device and determining a reference data rate according to configuration information of the flash memory module, the controller can determine whether the first bandwidth far exceeds a required bandwidth. If so, the bandwidth is dynamically reduced to a lower second bandwidth, thereby avoiding unnecessary power consumption.

Abstract: The present invention provides a control method of a flash memory controller. The flash memory controller is coupled between a host device and a flash memory module, and the flash memory controller is configured to receive a command from the host device to access the flash memory module; and the control method includes the steps of: setting a first bandwidth for communicating with the host device; receiving a specific command from the host device; and transmitting a bandwidth change request to the host device to negotiate with the host device to set a second bandwidth for communicating with the host device according to the specific command.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the method includes the steps of: using a first set of threshold voltages, a positively adjusted first set of threshold voltages and a negatively adjusted first set of threshold voltages to read the first logical page to obtain first readout information, second readout information and third readout information, respectively; selecting a second logical page of the physical page; using a second set of threshold voltage to read the second logical page to generate fourth readout information; adjusting the first set of threshold voltages to generate an adjusted first set of threshold voltages according to the first readout information, the second readout information, the third readout information and the fourth readout information; and using the adjusted first set of threshold voltages to read the first logical page of the flash memory module.

Abstract: The invention introduces a method for garbage collection (GC) in a flash storage device, performed by a processing unit, to include: considering data blocks whose hot-data scores are lower than a threshold as block candidates according to records in a hot-data scoring table; sorting the block candidates in ascending order according to valid page counts (VPCs) associated with the block candidates; starting from the candidate block with a smallest VPC, selecting source blocks from sorted block candidates in which valid user data can fill one destination block; and programming valid user data of the source blocks into a destination block in a flash module.

Abstract: The invention introduces a method for handling a garbage collection (GC) process, performed by a processing unit of a flash controller, to include: detecting that a portable storage device is inserted into a host equipment; obtaining a maximum transmission bandwidth of a host interface (I/F); determining that a transmission bandwidth of a flash I/F is higher than the maximum transmission bandwidth of the host I/F; and in response to a determination that the transmission bandwidth of the flash I/F is higher than the maximum transmission bandwidth of the host I/F, inserting operations of the GC process during an execution of a host command.

Abstract: A decoding method includes: providing channel value memory to store input data as a channel value; providing sign memory to store a sign value; providing gradient descent bit memory to store differential information of a channel value; providing variable node unit to generate a first output value and a second output value according to the channel value; converting first output value into a converted first output value from variable node domain into check node domain; providing check node unit to generate check-to-variable message according to the converted first output value or the sign value stored in the sign memory; converting the check-to-variable message into a converted check-to-variable message from check node domain into variable node domain and transmitting the converted check-to-variable message into the variable node domain; and, deciding output data according to channel value and differential information stored in gradient descent bit memory.

Abstract: Garbage collection technology for non-volatile memory is shown. Space allocation of the non-volatile memory is presented by a plurality of logical-to-physical address mapping sub-tables. The processor selects a plurality of source blocks and a destination block from the non-volatile memory for garbage collection. In order from the lowest to the highest logical address, the processor selects the logical-to-physical address mapping sub-tables in turn for use as a scan target, to perform a full scan of each logical-to-physical address mapping sub-table. In this way it identifies valid data in the source blocks, collects the valid data obtained from the source blocks, and programs the valid data to the destination block.

Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the method includes the steps of: using a first set of threshold voltages, a positively adjusted first set of threshold voltages and a negatively adjusted first set of threshold voltages to read a first logical page of a physical page of the flash memory module to obtain first readout information, second readout information and third readout information, respectively; decoding the first readout information, the second readout information and the third readout information to generate decoded data of the first logical page; and generating a LLR mapping table according to the decode data of the first logical page, the first readout information, the second readout information and the third readout information, for use when reading and decoding other logical pages.

Abstract: A data storage device is adaptively adjusted according to the sensed temperature. The data storage device has a first clock generator and a second clock generator, respectively generating a first clock and a second clock, which are selected by a controller to operate a nonvolatile memory. In response to the sensed temperature not exceeding a first threshold temperature, the controller selects the first clock to operate the non-volatile memory. In response to the sensed temperature exceeding the first threshold temperature, the controller alternately selects the first clock and the second clock to operate the non-volatile memory.

Abstract: A method for sorting commands in a memory controller includes receiving multiple commands from a host device and storing the commands in a command queue of the memory controller; and sequentially adding the commands in a handle list. The command queue includes multiple slots and each slot corresponds to one command, and step of sequentially adding the commands in the handle list further includes sorting the commands in the handle list based on an order of receiving the commands and a default priority of respective commands.

Abstract: The invention introduces a method for controlling executions of input-output (I/O) commands, performed by a processing unit, which includes: obtaining a current temperature of a device side; fetching I/O commands from a command queue during a fetching time period, and executing the I/O commands to read user data from the flash module, and/or program user data into the flash module in response to the current temperature of the device side exceeding a threshold; calculating a length of an actual execution time period for the I/O commands, and calculating a length of a pause time period according to the length of the actual execution time period after the I/O commands are executed completely; and not fetching and executing any I/O command in the command queue during the pause time period.

Abstract: A decoding method includes: using a syndrome calculation check circuit to calculate a syndrome value of variable node Vi of a parity check matrix based on multiple input bits; rotating the syndrome value of variable node Vi into the direction of variable node Vi+1 to generate an estimated syndrome value of variable node Vi+1; rotating the syndrome value of variable node Vi?1 into the direction of variable node Vi?? to generate a rotated syndrome information; performing a weighted-sum calculation based on multiple rotated syndrome information to generate a flipping function value; and comparing the flipping function value with a flipping threshold to generate a flipping result; the syndrome calculation check circuit determines whether to modify/flip a specific bit according to the flipping result.

Abstract: A decoding method includes: generating a variable-to-check message and a log-likely ratio according a specific codeword; converting the variable-to-check message from variable node domain into check node domain to generate a converted variable-to-check message; generating a check-to-variable message according to the converted variable-to-check message; converting the check-to-variable message from check node domain into variable node domain to generate a converted check-to-variable message; updating the variable-to-check message and the log-likely ratio based on the converted check-to-variable message; performing a hard decision according to the log-likely ratio to determine whether flip bit(s); and, for specific data to be stored into a first memory macro, enabling a write operation of a portion of first physical sub-memories and disabling a write operation of another portion of first physical sub-memories.

Abstract: The invention introduces a method for performing a sudden power off recovery (SPOR) process, performed by a processing unit of a flash controller, to include: performing operations for the SPOR process after regaining power; and performing operations for a reduced garbage collection (GC) process. An execution time of the operations for the SPOR process and the reduced GC process is limited to a preset time that a host side waits for a completion of the SPOR process by the flash controller.

Abstract: The present invention provides a method for controlling a flash memory module. The method includes the steps of: after the flash memory module is powered on, determining whether the flash memory module encountered an abnormal power failure before the flash memory module is powered on; if the flash memory module encounters the abnormal power failure before the flash memory module is powered on, determining a last super block written by the flash memory module before powering on, where the super block includes multiple first blocks; determining a last rewritten page of the super block; determining a check range of the super block according to the last written page of the super block; determining a data weak region of the super block by reading the pages of the check range; and moving data in the weak data region to other regions of the super block or to another super block.

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Abstract: A flash memory controller includes a controller circuit and a scheduler circuit. The controller circuit receives a multi-plane read command signal sent from a host device to respectively read data of storage pages, corresponding to the carried address information, on multiple memory planes within a flash memory. The controller circuit stores the first read commands in the first pending list and stores the second read commands in the second pending list. The scheduler circuit reorders the read commands stored in the first and second pending lists to make first data output time intervals be staggered and not overlap with second data output time intervals.