Abstract: The invention introduces a method for producing solid state disk (SSD) devices, performed by a processing unit of a production host, to include steps of: loading a port-mapping configuration table including location information regarding each port connected to the production host; comparing location information in a hardware description file with the location information in the port-mapping configuration table to determine which ports that SSD devices are connected to; displaying a graphical user interface (GUI) on a displayer to indicate which ports are connected by SSD devices; and when an SSD device connected to one port that fails to activate, updating the GUI to display information indicating that an SSD device connected to the corresponding port that fails to activate.
Abstract: A method for performing access management of a memory device with aid of a Universal Asynchronous Receiver-Transmitter (UART) connection and associated apparatus are provided. The method may include: utilizing a UART of a memory controller within the memory device to receive a set of intermediate commands corresponding to a set of operating commands through the UART connection between the memory device and a host device, wherein before sending the set of intermediate commands to the controller through the UART connection, the host device converts the set of operating commands into the set of intermediate commands; converting the set of intermediate commands into the set of operating commands according to a command mapping table; and accessing a non-volatile (NV) memory within the memory device with the set of operating commands for the host device, and sending a response to the host device through the UART connection.
Abstract: The invention introduces an apparatus for handling flash physical-resource sets, at least including a random access memory (RAM), a processing unit and an address conversion circuit. The RAM includes multiple segments of temporary space and each segment thereof stores variables associated with a specific flash physical-resource set. The processing unit accesses user data of a flash physical-resource set when executing program code of a Flash Translation Layer (FTL). The address conversion circuit receives a memory address issued from the FTL, converts the memory address into a relative address of one segment of temporary space associated with the flash physical-resource set and outputs the relative address to the RAM for accessing a variable of the associated segment of temporary space.
Abstract: A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.
Abstract: The present invention provides a method for access a flash memory module, wherein the method includes the steps of: sending a read command to the flash memory module to read a plurality of memory cells of at least one word line of the flash memory module by using a plurality of read voltages, wherein each memory cell is configured to store a plurality of bits, each memory cell has a plurality of states, the states are used to indicate different combinations of the plurality of bits; obtaining readout information from the flash memory module; analyzing the readout information to determine numbers of the states of the memory cells; determining if the memory cells are balance or unbalance according the numbers of the states of the memory cells to generate a determination result; and referring to the determination result to adjust voltage levels of the plurality of read voltages.
Abstract: The present invention provides a memory controller configured to access a plurality of channels, wherein each of the channels includes a plurality flash memory chips, and the memory controller includes a flash translation layer and a plurality of control modules. The flash translation layer is configured to generate commands with corresponding physical addresses of at least one of the channels. The plurality of control modules are connected to the plurality of channels, respectively, and each of the control modules operates independently to receive the corresponding command with the corresponding physical address from the flash translation layer, to access the flash memory chips within the corresponding channels.
Abstract: The invention introduces a method for verifying memory interface, performed by a processing unit, to include: driving a physical layer of a memory interface to pull-high or pull-low a signal voltage on each Input-Output (IO) pin thereof to a preset level according to a setting; obtaining a verification result corresponding to each IO pin from the memory interface; and storing each verification result in a static random access memory (SRAM), thereby enabling a testing host to obtain each verification result of the SRAM through a test interface. The testing host may examine each verification result to know whether any unexpected error has occurred in signals on the IO pins of the memory interface.
Abstract: A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information are provided. The method may include: sending internal information of the memory device to a host device, to allow the host device to store the internal information of the memory device in a memory within the host device as host side table information at the host device; generating and storing multiple entries of at least one address mapping control table into a random access memory (RAM) as at least one portion of device side table information at the memory device; determining at least two physical addresses associated with at least two logical addresses according to the at least one address mapping control table; and reading data from the NV memory according to the at least two physical addresses.
Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
April 28, 2021
Date of Patent:
November 15, 2022
Silicon Motion, Inc.
Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
Abstract: Disclosed is a sideband signal adjustment system including an M.2 interface module containing a first power supply voltage pin and a second power supply voltage pin, a switching module, and a control module. When the control module detects that the second power pin receives a second power voltage, the switching module electrically connects to the second power supply voltage pin, and the control module receives or sends a second sideband signal with the same voltage level as the second power supply voltage through the M.2 interface module. When the control module detects that the first power supply voltage pin receives the first power supply voltage different from the second power voltage, the switching module electrically connects to the first power supply voltage pin, and the control module receives or sends a first sideband signal with the same voltage level as the first power supply voltage through the M.2 interface module.
Abstract: A method of managing a garbage collection (GC) operation on a flash memory includes: setting a GC starting threshold, wherein the GC starting threshold indicates a predetermined spare block number that is higher than a target spare block number of spare blocks maintained by a flash translation layer (FTL) of the flash memory; determining whether to start the GC operation according to a current number of spare blocks in the flash memory and the GC starting threshold; and performing the GC operation on a source block in the flash memory when the current number of spare blocks is lower than or equal to the GC starting threshold.
Abstract: A storage device includes a flash memory array and a controller. The flash memory array stores a plurality of user data. After the controller finishes initialization, the controller accesses the user data stored in the flash memory array according to a plurality of host commands and an H2F mapping table, and records a plurality of address information about the user data in a powered-ON access table.
Abstract: The invention introduces a non-transitory computer program product for scheduling execution of host commands when executed by a processing unit of a flash controller. Space of a random access memory of the flash controller is allocated for a first queue and a second queue, and the first queue stores the host commands issued by a host side in an order of time when the host commands arrive to the flash controller. The non-transitory computer program product includes program code to: migrate one or more host write commands from the top of the first queue to the second queue in an order of time when the host write commands arrive to the flash controller until the top of the first queue stores a host read command; fetch the host read command from the top of the first queue; execute the host read command to read user data from a flash module; and reply to the host side with the user data.
December 15, 2020
Date of Patent:
November 8, 2022
SILICON MOTION, INC.
Shou-Wei Lee, Chun-Chieh Kuo, Hsueh-Chun Fu
Abstract: The present invention provides an electronic device, wherein the electronic device includes a flash memory module and a flash memory controller. The flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, and each block includes a plurality of pages, and the flash memory controller is configured to access the flash memory module. In the operations of the electronic device, when the flash memory controller sends a read command to the flash memory module to ask for data on at least one page, the flash memory module uses a plurality of read voltages to read each memory cell of the at least one page to obtain multi-bit information of each memory cell, and the flash memory module transmits the multi-bit information of each memory cell of the at least one page to the flash memory controller.
Abstract: The present invention provides a method for accessing a flash memory module, wherein the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of blocks, each block comprises a plurality of pages, and the method comprises: sending a read command to the flash memory module to ask for data on at least one memory unit; and analyzing state information of a plurality of memory cells of the memory unit based on information from the flash memory module to determine a decoding method adopted by a decoder.
Abstract: The invention relates to a method, a non-transitory computer-readable storage medium, and an apparatus for executing an embedded multi-media card (eMMC) command. The method is performed by a processing unit of a flash controller to include: receiving an eMMC command from a host side; and performing a first function associated with a host performance acceleration (HPA) mode according to content of reserved bits of the eMMC command. The HPA mode allows the host side to allocate space in a system memory as an HPA buffer. The HPA buffer stores logical-block-address to physical-block-address (L2P) mapping entries obtained from the flash controller, and each L2P mapping entry stores information indicating which physical address that user data of a corresponding logical address is physically stored in a flash device, thereby enabling the host side to issue an HPA read command carrying the physical address to the flash controller.
Abstract: The invention introduces an apparatus for segmenting a data stream, installed in a physical layer, to include a host interface, a data register and a boundary detector. The data register is arranged to operably store data received from the host side through the host interface. The boundary detector is arranged to operably detect the content of a data register. When the data register includes a special symbol, the boundary detector outputs a starting address that the special symbol is stored in the data register to an offset register to update a value stored in the offset register, thereby enabling a stream splitter to divide data bits of the data register according to the updated value of the offset register.
Abstract: The present invention provides a flash memory controller, wherein the flash memory controller is arranged to access a flash memory module, and the flash memory controller includes a ROM, a microprocessor and a timer. The ROM stores a program code, the microprocessor is configured to execute the program code to control the access of the flash memory module, and the timer is used to generate time information. In the operations of the flash memory controller, the microprocessor refers to the time information to perform dummy read operations upon at least a portion of the blocks, wherein the dummy read operations are not triggered by read commands from a host device.
June 23, 2021
Date of Patent:
November 1, 2022
Silicon Motion, Inc.
Jian-Dong Du, Chia-Jung Hsiao, Tsung-Chieh Yang
Abstract: A control method is applied to a flash memory controller, which includes the following steps: creating a write time table, wherein the write time table records block numbers of blocks having data stored therein and corresponding first time and second time; referring to the write time table to determine whether there is at least one first block in the flash memory module whose first time is earlier than a first threshold, and if so, recording the at least one first block into an expired block table; referring to the write time table to determine whether there is at least one second block in the flash memory module whose second time is earlier than a second threshold, and if so, recording the at least one second block into the expired block table; and referring to the expired block table to perform an expired block recycling operation.
Abstract: A memory device includes a non-volatile (NV) memory including a plurality of NV memory elements. A method for performing programming management of the NV memory includes: setting a programming sequence of the NV memory elements; determining a selection interval between each of the NV memory elements according to the programming sequence and a serial number of each of the NV memory elements; for a target NV memory element of the plurality of NV memory elements in the programming sequence, determining a serial number of an immediately previous NV memory element in the programming sequence according to the selection interval and a serial number of the target NV memory element; determining whether the immediately previous NV memory element is in a busy state; and only when the immediately previous NV memory element is not in the busy state, programming the target NV memory element.