Abstract: An encoder includes: a barrel shifter module, a circulant convolution calculation circuit and a compensation circuit. The barrel shifter module is arranged to process multiple data blocks to sequentially generate multiple partial parity blocks. The circulant convolution calculation circuit is coupled to the barrel shifter module and arranged to perform a circulant convolution operation upon the multiple partial parity blocks to generate a plurality of convolution results. The compensation circuit is coupled to the circulant convolution calculation circuit and arranged to perform a compensation operation upon the plurality of convolution results to generate a plurality of parity blocks in a causal manner, wherein the plurality of multiple parity blocks are written into a flash memory.

Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values. The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

Abstract: The present invention provides a glitch filter including a delay chain, a first control circuit, a second control circuit, a first transistor, a second transistor, a first switch and the second switch. The delay chain is configured to delay an input signal to generate a delayed input signal. The first control circuit is configured to receive the input signal and the delayed input signal to generate a first control signal. The second control circuit is configured to receive the input signal and the delayed input signal to generate a second control signal. The first transistor and the second transistor receive the input signal to generate an output signal. The first switch is configured to selectively couple a supply voltage to the first transistor according to the first control signal. The second switch is configured to selectively couple a ground voltage to the second transistor according to the second control signal.

Abstract: The disclosure introduces a flash controller, configured to: perform operations for a sudden power off recovery (SPOR) process after regaining power; perform operations for a garbage collection (GC) process after the operations for the SPOR process have completed; and exit the GC process when an execution time of the GC process has exceeded a predetermined time.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module. The flash memory controller includes the steps of: selecting a block within the flash memory module, wherein the block is a blank block; writing data into the block; after the block is full, determining an amount of data from a host device written into the block, wherein the host device is external to the flash memory controller; and determining if the host device is performing a sequential write operation to write the data with consecutive logical addresses into the block according to a size of the block and the amount of data from the host device written into the block.

Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the method includes the steps of: using a first set of threshold voltages, a positively adjusted first set of threshold voltages and a negatively adjusted first set of threshold voltages to read the first logical page to obtain first readout information, second readout information and third readout information, respectively; selecting a second logical page of the physical page; using a second set of threshold voltage to read the second logical page to generate fourth readout information; adjusting the first set of threshold voltages to generate an adjusted first set of threshold voltages according to the first readout information, the second readout information, the third readout information and the fourth readout information; and using the adjusted first set of threshold voltages to read the first logical page of the flash memory module.

Abstract: A method for executing error recovery in a flash memory includes: retrieving a codeword from a data group in the flash memory; performing a first horizontal decoding on the retrieved codeword; in response to a failure of the first horizontal decoding, performing an exclusive-OR (XOR) operation according to the retrieved codeword and XOR-derived parity data in the data group to generate error likelihood information for the retrieved codeword; updating soft information corresponding to the retrieved codeword based on the error likelihood information; and performing a second horizontal decoding on the retrieved codeword based on the updated soft information.

Abstract: A method for performing enhanced data protection of a memory device with aid of in-channel coding and associated apparatus are provided, where the memory device may include a memory controller and a non-volatile (NV) memory, and undergo a reflow process for mounting the memory device onto a PCB of a host device within an electronic device. The method may include: during a system level initialization of the electronic device, utilizing the memory controller to start performing expansion-to-non-expansion storage format conversion on preloaded data in the NV memory, wherein the preloaded data has been preloaded into the NV memory in a first storage format, for inserting extra parity information obtained from the in-channel coding among multiple data chunks; and during the expansion-to-non-expansion storage format conversion, converting the preloaded data from the first storage format into a second storage format, for collecting the multiple data chunks and releasing partial storage space.

Abstract: The invention introduces a method for operating hybrid NAND flash units, performed by a processing unit of a flash controller, to include: connecting to a flash module including a first NAND flash unit, a second NAND flash unit, a third NAND flash unit and a fourth NAND flash unit; and programming user data obtained from a host side into the flash module. First areas of single level cell (SLC) regions of the first to the fourth NAND flash units jointly provide cache space for triple level cell (TLC) regions of the first and third NAND flash units, and second areas of the SLC regions of the first to the fourth NAND flash units jointly provide cache space for quad-level cell (QLC) regions of the second and the fourth NAND flash units.

Abstract: Disclosed is a memory controller, a method for controlling a memory controller and a memory device. The memory controller comprises a first interface circuit configured to communicate with a host, a second interface circuit comprising at least one pin, and a control circuit coupled to the first and second interface circuits. Wherein the control circuit is configured to perform an initialization operation via the first interface circuit, and control the at least one pin of the second interface circuit to output a signal indicating a status of the initialization operation. Wherein the signal comprises a dynamic pattern during a processing phase of the initialization operation and a static pattern corresponding to an operation result during a completion phase of the initialization operation.

Abstract: A data storage device that performs instruction scheduling at the device side. The data storage device has a non-volatile memory, and a controller configured to operate the non-volatile memory in response to requests from the host side. The controller has an instruction cache operative to cache instructions issued from the host side. Based on information carried by the instructions, the controller schedules and executes the instructions to operate the non-volatile memory.

Abstract: The disclosure introduces a method for handling a garbage collection (GC) process, performed by a processing unit of a flash controller, to include: detecting that a portable storage device is inserted into a host equipment; operating the portable storage device in a working state; determining whether a transmission bandwidth of a flash I/F is higher than a maximum transmission bandwidth of a host interface (I/F); if so, inserting operations of the GC process during an execution of a host command in the working state; resetting a working expiration timer for counting a specified period of time each time after receiving any host command; and in response to detecting that the working expiration timer reaches the specified period of time, causing the portable storage device to leave the working state and enter a power saving state.

Abstract: A decoding method includes: receiving and storing input data as a channel value in a channel value memory in a form of codeword; generating a posterior probability and a variable-to-check message according to a specific chunk of the channel value; converting the variable-to-check message from variable node domain into check node domain to generate a converted variable-to-check message; using a check node unit to generate a check-to-variable message according to the converted variable-to-check message; converting the check-to-variable message from check node domain into variable node domain to generate a converted check-to-variable message; determining whether to flip at least one bit of the specific chunk according to the posterior probability; and, determining whether to ignore and skip execution of decoding calculation for the specific chunk in a next iterative decoding operation according to whether a decoding calculation result in a current iterative decoding operation matches with a specific condition.

Abstract: The present invention provides a decoding method, which includes steps of: receiving data from a flash memory module; generating syndromes corresponding to the data according to the data and a parity check matrix; storing decoding information corresponding to only a portion of the data into a memory; iteratively updating the syndromes and the decoding information stored in the memory until the updated syndromes meet a specific condition; and generating decoded data according to the updated syndromes and the updated decoded information.

Abstract: Provided are a data storage device and a decoding combination selecting method. The data storage device includes a non-volatile memory and a processing circuit. The non-volatile memory includes a plurality of blocks. Each block includes a plurality of pages. A decoding combination selecting method is executed by the processing circuit to include: periodically reading a page in the non-volatile memory to update state parameters of a first block including the page in a block state table; and selecting one of a plurality of decoding combinations based on the state parameters of the first block in the block state table to decode the first block. The state parameters include a charge leakage degree value, a potential offset degree value, a first offset voltage and a second offset voltage, and a first bit number and a second bit number respectively corresponding to the first offset voltage and the second offset voltage.

Abstract: A method for performing data protection control of a memory device with aid of selective soft-bit transmission and associated apparatus are provided, where the memory device may include a memory controller and a non-volatile (NV) memory. The method may include: sending at least one read command as well as a controller-side indication, the controller-side indication for selectively enabling the selective soft-bit transmission at the NV memory, to the NV memory for obtaining soft-decoding information regarding a first page within a first block among the plurality of blocks, wherein the first page is arranged to store first data; and receiving the soft-decoding information as well as a memory-side indication from the NV memory, wherein the memory-side indication at a first cycle is arranged to indicate whether the NV memory is going to transmit at least one soft bit at a second cycle, the second cycle coming after the first cycle.

Abstract: A decoding method includes: using a syndrome calculation check circuit to calculate a syndrome value of variable node Vi of a parity check matrix based on multiple input bits; rotating the syndrome value of variable node Vi into the direction of variable node Vi+1 to generate an estimated syndrome value of variable node Vi+1; rotating the syndrome value of variable node Vi?1 into the direction of variable node Vi+? to generate a rotated syndrome information; performing a weighted-sum calculation based on multiple rotated syndrome information to generate a flipping function value; and comparing the flipping function value with a flipping threshold to generate a flipping result; the syndrome calculation check circuit determines whether to modify/flip a specific bit according to the flipping result.

Abstract: A decoding method includes: generating a variable-to-check message and a log-likely ratio according a specific codeword; converting the variable-to-check message from variable node domain into check node domain to generate a converted variable-to-check message; generating a check-to-variable message according to the converted variable-to-check message; converting the check-to-variable message from check node domain into variable node domain to generate a converted check-to-variable message; updating the variable-to-check message and the log-likely ratio based on the converted check-to-variable message; performing a hard decision according to the log-likely ratio to determine whether flip bit(s); and, for specific data to be stored into a first memory macro, enabling a write operation of a portion of first physical sub-memories and disabling a write operation of another portion of first physical sub-memories.