Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the method includes the steps of: using a first set of threshold voltages, a positively adjusted first set of threshold voltages and a negatively adjusted first set of threshold voltages to read a first logical page of a physical page of the flash memory module to obtain first readout information, second readout information and third readout information, respectively; decoding the first readout information, the second readout information and the third readout information to generate decoded data of the first logical page; and generating a LLR mapping table according to the decode data of the first logical page, the first readout information, the second readout information and the third readout information, for use when reading and decoding other logical pages.

Abstract: A data storage device is adaptively adjusted according to the sensed temperature. The data storage device has a first clock generator and a second clock generator, respectively generating a first clock and a second clock, which are selected by a controller to operate a nonvolatile memory. In response to the sensed temperature not exceeding a first threshold temperature, the controller selects the first clock to operate the non-volatile memory. In response to the sensed temperature exceeding the first threshold temperature, the controller alternately selects the first clock and the second clock to operate the non-volatile memory.

Abstract: A method for sorting commands in a memory controller includes receiving multiple commands from a host device and storing the commands in a command queue of the memory controller; and sequentially adding the commands in a handle list. The command queue includes multiple slots and each slot corresponds to one command, and step of sequentially adding the commands in the handle list further includes sorting the commands in the handle list based on an order of receiving the commands and a default priority of respective commands.

Abstract: The invention introduces a method for controlling executions of input-output (I/O) commands, performed by a processing unit, which includes: obtaining a current temperature of a device side; fetching I/O commands from a command queue during a fetching time period, and executing the I/O commands to read user data from the flash module, and/or program user data into the flash module in response to the current temperature of the device side exceeding a threshold; calculating a length of an actual execution time period for the I/O commands, and calculating a length of a pause time period according to the length of the actual execution time period after the I/O commands are executed completely; and not fetching and executing any I/O command in the command queue during the pause time period.

Abstract: A decoding method includes: using a syndrome calculation check circuit to calculate a syndrome value of variable node Vi of a parity check matrix based on multiple input bits; rotating the syndrome value of variable node Vi into the direction of variable node Vi+1 to generate an estimated syndrome value of variable node Vi+1; rotating the syndrome value of variable node Vi?1 into the direction of variable node Vi?? to generate a rotated syndrome information; performing a weighted-sum calculation based on multiple rotated syndrome information to generate a flipping function value; and comparing the flipping function value with a flipping threshold to generate a flipping result; the syndrome calculation check circuit determines whether to modify/flip a specific bit according to the flipping result.

Abstract: A decoding method includes: generating a variable-to-check message and a log-likely ratio according a specific codeword; converting the variable-to-check message from variable node domain into check node domain to generate a converted variable-to-check message; generating a check-to-variable message according to the converted variable-to-check message; converting the check-to-variable message from check node domain into variable node domain to generate a converted check-to-variable message; updating the variable-to-check message and the log-likely ratio based on the converted check-to-variable message; performing a hard decision according to the log-likely ratio to determine whether flip bit(s); and, for specific data to be stored into a first memory macro, enabling a write operation of a portion of first physical sub-memories and disabling a write operation of another portion of first physical sub-memories.

Abstract: The invention introduces a method for performing a sudden power off recovery (SPOR) process, performed by a processing unit of a flash controller, to include: performing operations for the SPOR process after regaining power; and performing operations for a reduced garbage collection (GC) process. An execution time of the operations for the SPOR process and the reduced GC process is limited to a preset time that a host side waits for a completion of the SPOR process by the flash controller.

Abstract: The present invention provides a method for controlling a flash memory module. The method includes the steps of: after the flash memory module is powered on, determining whether the flash memory module encountered an abnormal power failure before the flash memory module is powered on; if the flash memory module encounters the abnormal power failure before the flash memory module is powered on, determining a last super block written by the flash memory module before powering on, where the super block includes multiple first blocks; determining a last rewritten page of the super block; determining a check range of the super block according to the last written page of the super block; determining a data weak region of the super block by reading the pages of the check range; and moving data in the weak data region to other regions of the super block or to another super block.

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Abstract: A flash memory controller includes a controller circuit and a scheduler circuit. The controller circuit receives a multi-plane read command signal sent from a host device to respectively read data of storage pages, corresponding to the carried address information, on multiple memory planes within a flash memory. The controller circuit stores the first read commands in the first pending list and stores the second read commands in the second pending list. The scheduler circuit reorders the read commands stored in the first and second pending lists to make first data output time intervals be staggered and not overlap with second data output time intervals.

Abstract: An error handling method for use in a flash memory includes: in response to read data on which a decoding failure occurs or written data on which a programming failure occurs, determining verification data corresponding to the read data or the written data; according to the verification data, selecting data to be moved from the flash memory; and performing a data movement operation to move the data to be moved to a target storage space in the flash memory.

Abstract: A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.

Abstract: A flash memory controller includes a controller circuit and a scheduler circuit. The controller circuit receives a multi-plane read command signal sent from a host device to respectively read data of storage pages, corresponding to the carried address information, on multiple memory planes within a flash memory. The controller circuit stores the first read commands in the first pending list and stores the second read commands in the second pending list. The scheduler circuit reorders the read commands stored in the first and second pending lists to make first data output time intervals be staggered and not overlap with second data output time intervals.

Abstract: A block cipher method of a flash memory controller includes: encrypting a seed value to generate an encrypted seed value in a first/second block cipher mode according to a second key; multiplying the encrypted seed value with ?j according to a mode selection signal to generate a j-th multiplication result; performing a first XOR operation upon the j-th multiplication result and a j-th plaintext block to generate a first XOR result; encrypting the first XOR result to generate an encrypted XOR result in the first/second block cipher mode according to a first key; and, performing a second XOR operation upon the j-th multiplication result and the encrypted XOR result to generate a second XOR result as a j-th ciphertext block; the multiplying step operating in the first/second block cipher mode is determined by either the mode selection signal generated from a microcontroller or recorded in a 0-th plaintext block.

Abstract: The present invention provides a control method of a flash memory controller. The flash memory controller is coupled between a host device and a flash memory module, and the flash memory controller is configured to receive a command from the host device to access the flash memory module; and the control method comprises: setting a first bandwidth for communicating with the host device; determining a reference data rate according to configuration information of the flash memory module; determining if the first bandwidth far exceeds a required bandwidth according to the reference data rate; and if it is determined that the first bandwidth far exceeds the required bandwidth, setting a second bandwidth lower than the first bandwidth, for communicating with the host device.

Abstract: A decoding method includes: providing channel value memory to store input data as a channel value; providing sign memory to store a sign value; providing gradient descent bit memory to store differential information of a channel value; providing variable node unit to generate a first output value and a second output value according to the channel value; converting first output value into a converted first output value from variable node domain into check node domain; providing check node unit to generate check-to-variable message according to the converted first output value or the sign value stored in the sign memory; converting the check-to-variable message into a converted check-to-variable message from check node domain into variable node domain and transmitting the converted check-to-variable message into the variable node domain; and, deciding output data according to channel value and differential information stored in gradient descent bit memory.

Abstract: A method for performing access control of a memory device with aid of expander architecture and associated apparatus are provided, where the memory device may include a memory controller and a non-volatile (NV) memory. The method may include: sending at least one command from the memory controller to the NV memory through an input-output-expander (IO-expander) circuit, with the IO-expander circuit being coupled between the memory controller and the NV memory, in order to start performing at least one access operation on the plurality of NV memory elements via multiple channels, respectively; and during performing any access operation among the at least one access operation, utilizing the IO-expander circuit to expand IO control of the memory controller over the NV memory, for accessing at least one NV memory element corresponding to any sub-channel among a plurality of sub-channels, the plurality of sub-channels split from a single channel among the multiple channels.

Abstract: A coding method of a flash memory controller includes: performing a local encoding operation upon a data unit to be written into a portion of a page unit of the flash memory device and to perform a global encoding operation upon multiple data units to be written into the page unit according to a coding matrix so as to generate and write error correction code data into the page unit; performing a local decoding operation upon the data unit read from the portion of the page unit and to perform a global decoding operation upon the multiple data units read from the page unit according to the error correction code data corresponding to the coding matrix to obtain correct data of the page unit; and, dynamically determining the coding matrix to dynamically select a coding mode.

Abstract: A method for performing data protection control of a memory device with aid of selective soft-bit transmission and associated apparatus are provided, where the memory device may include a memory controller and a non-volatile (NV) memory. The method may include: sending at least one read command as well as a controller-side indication, the controller-side indication for selectively enabling the selective soft-bit transmission at the NV memory, to the NV memory for obtaining soft-decoding information regarding a first page within a first block among the plurality of blocks, wherein the first page is arranged to store first data; and receiving the soft-decoding information as well as a memory-side indication from the NV memory, wherein the memory-side indication at a first cycle is arranged to indicate whether the NV memory is going to transmit at least one soft bit at a second cycle, the second cycle coming after the first cycle.