Abstract: A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information are provided. The method may include: sending internal information of the memory device to a host device, to allow the host device to store the internal information of the memory device in a memory within the host device as host side table information at the host device; generating and storing multiple entries of at least one address mapping control table into a random access memory (RAM) as at least one portion of device side table information at the memory device; determining at least two physical addresses associated with at least two logical addresses according to the at least one address mapping control table; and reading data from the NV memory according to the at least two physical addresses.

Abstract: The invention introduces a method for configuring a reliable command, performed by a flash controller, including: issuing a read ID command to a flash module; and parsing an opcode of a reliable command from reserved bytes in reply data for the read ID command, where the reliable command is used to direct the flash module for access to data in a single level cell (SLC) mode.

Abstract: A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for data access in response to a host discard command. The method includes: allocating space in a random access memory (RAM) for an expanded discard table; receiving the host discard command from a host side; appending new entries each including one first logical address to the expanded discard table; and setting a start-address register and/or an end-address register in a performance engine for redefining an address range in the RAM that stores the expanded discard table, thereby enabling the performance engine to search the expanded discard table in the address range in the RAM for determining whether a specific logical address of user data is no longer used.

Abstract: A method for performing data access performance shaping of a memory device and associated apparatus are provided. The method may include: receiving a plurality of host commands from a host device, for performing data access on the NV memory according to the plurality of host commands; and monitoring the plurality of host commands to control respective performance metrics of a plurality of access control groups of the memory device with a dual-state leaky bucket (LB) model, wherein regarding any access control group, for example: determining at least one first performance metric according to at least one first command to be a first LB fill level of a dual-state LB; in response to the first LB fill level being below a state threshold, determining the dual-state LB to be in a first predetermined state, and configuring the dual-state LB to have a first predetermined drain rate, for dynamically adjusting performance quota.

Abstract: A solution for deteriorated non-volatile memory is shown. When determining that raw data read from the non-volatile memory is undesirable data, the controller updates a deterioration table to record a deteriorated logical address of the raw data that is the undesirable data. When performing garbage collection from a source block associated with the deteriorated logical address to a destination block and determining that the deteriorated logical address is listed in the deterioration table, the controller invalidates target data stored in the source block and mapped to the deteriorated logical address, without moving the target data from the source block to the destination block in the garbage collection.

Abstract: A method for evaluating a margin of at least one parameter utilized by a transmission interface includes: step (A) setting a value of a first parameter utilized by a host device to a first test value selected from a first group; (B) setting a value of a second parameter utilized by a data storage device to a second test value selected from a second group; (C) controlling the data storage device to perform a predetermined testing procedure to test whether the data storage device functions normally when the first test value and the second test value are applied; and (D) changing the first test value or the second test value and re-performing steps (A) to (C), wherein step (D) is repeatedly performed until all the test values in the first group and the second group have been tested.

Abstract: A data processing method includes reading a memory device in response to a read command to respectively read multiple portions of predetermined data; respectively writing the portions in a buffer memory to complete data transfers of the portions of the predetermined data; sequentially providing access information corresponding to each portion of the predetermined data in response to completion of the data transfer of the corresponding portion; obtaining the access information of the predetermined data and accordingly generating multiple descriptors in chronological order of obtaining the access information; receiving and buffering the descriptors in a descriptor pool; sequentially selecting a latest descriptor from the descriptor pool according to a tag value and providing the latest descriptor to a direct memory access engine; and reading the buffer memory according to the latest descriptor to obtain at least a portion of the predetermined data by the direct memory access engine.

Abstract: The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, the flash memory module includes a plurality of planes, and each plane includes a plurality of blocks; and the control method includes the steps of: after the flash memory controller is powered on, reading a first code bank from a specific block of the plurality of blocks; storing the first code bank into a buffer memory; executing the first code bank to manage the flash memory module; when the flash memory controller starts a code bank swapping operation, trying to read a second code bank from a super block; if the second code bank is read successfully, storing the second code bank into the buffer memory to replace the first code bank; and executing the second code bank to manage the flash memory module.

Abstract: A method for performing access management of a memory device with aid of serial number assignment timing control and associated apparatus are provided. The method includes: managing a plurality of spare blocks with a spare pool; popping a first block from the spare pool to be a host data block, and performing first subsequent operations, wherein the host data block is arranged to receive data from a host device, and serial number assignment of the host data block corresponds to a timing of fully programing the host data block; and popping a second block from the spare pool to be a garbage collection (GC) destination block, and performing second subsequent operations, wherein the GC destination block is arranged to receive data from a GC source block during a GC procedure, and serial number assignment of the GC destination block corresponds to a timing of starting using the GC destination block.

Abstract: A method of caching mapping table for use in a flash memory device having a flash memory controller and a flash memory is provided. The method includes: in response to a host read command, determining whether a group of a logical-to-physical (L2P) required by handling the host read command has been loaded to a DRAM of the flash memory controller; if the required group of the L2P mapping table has not been loaded to the DRAM, loading the required group of the L2P mapping table from the flash memory to a SRAM of the flash memory controller; directly accessing the SRAM to obtain an L2P address associated with the host read command from the required group of the L2P mapping table; and performing a read operation on the flash memory in response to the host read command according to the obtained L2P address.

Abstract: A memory controller coupled to a memory device and configured to control access operations of the memory device includes a host interface and a microprocessor. The microprocessor is coupled to the host interface and configured to set a value of a predetermined parameter to a specific value after the memory controller powers up and start to perform a link flow to try to establish a transmission link via the host interface. The predetermined parameter is one of a plurality of capability parameters of the host interface and the predetermined parameter is related to reception of the host interface. After the link flow is completed, the microprocessor is further configured to identify an object device with which the host interface establishes the transmission link according to the specific value and at least one of a plurality of attribute parameters associated with the transmission link.

Abstract: A flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller into a simplified command sequence so as to reduce the waiting time period of the command transmission and improve the performance of flash memory.

Abstract: A method of a flash memory controller includes: providing an input/output (I/O) circuit coupled to a flash memory device through a specific communication interface; and, controlling a processor sending a specific read command or a data toggle command through the I/O circuit and the specific communication interface into the flash memory device, to make the flash memory device perform a data toggle operation to control the flash memory device’s data register selecting and transferring a first data unit and a second data unit to the flash memory device’s I/O control circuit to make the I/O control circuit sequentially transmit the first data unit and the second data unit to the flash memory controller through the specific communication interface in response to the specific read command or the data toggle command.

Abstract: An electronic device includes a data storage device and a host device. The host device is coupled to the data storage device via a predetermined interface and includes a processor. The processor dynamically adjusts a data transfer speed of the predetermined interface according to a data processing speed required by data to be read from or written to the data storage device.

Abstract: Power recovery for data storage devices with an efficient space trimming technology is shown. A controller scans a non-volatile memory according to a programming order, collects a sequence of trimming information flags, and interprets a sequence of storage information scanned from the non-volatile memory to identify logical addresses and trimming code. Based on the logical addresses, a host-to-device mapping (H2F) table is rebuilt. Based on the trimming code, information of medium-length trimming and information of long-length trimming are recognized from a storage area of the non-volatile memory. According to the trimming information for medium-length trimming, dummy mapping data is programmed to the H2F table. According to the trimming information for long-length trimming, a trimming bitmap (TBM) is rebuilt. Each bit in the TBM marks space trimming of a first length.

Abstract: A method for managing a memory apparatus including a plurality of non-volatile (NV) memory elements includes: programming a physical block of a specific NV memory element, including: receiving a host command from a host; obtaining a host address and data from the host command; and linking the host address to a page of a physical block of the specific NV memory element and storing the data into the physical block. Before the pages of the physical block are fully programmed, a temporary local page linking address table is stored and is updated each time a linking relationship is changed. When the memory apparatus is to be shut down, the temporary local page linking address table is written to the specific NV memory element; and when the memory apparatus begins a start-up process, a global page address linking table is built by reading the local page address linking table.

Abstract: The present invention provides a control method of the flash memory controller. In the control method, after receiving a deallocate command from a host device, the flash memory controller will update a valid page count table, a detailed valid page count table and/or a zone valid page count table according to deallocate command, for the flash memory controller to efficiently and quickly determine if any one of the zones does not have any valid data, so that the flash memory controller can recommend the host device to send a reset command to reset the zone.

Abstract: A data storage device includes a memory device including multiple memory blocks corresponding to multiple logical units and a memory controller. The memory controller accesses the memory device and updates content of an activated count table in response to a command issued by a host device. One or more sub-regions to be activated are identified in the command. The activated count table includes a plurality of fields each recording an activated count associated with one sub-region. The memory controller updates content of the activated count table by increasing one or more activated counts associated with the one or more sub-regions identified in the command. The memory controller further selects at least one sub-region according to the content of the activated count table and performs a data rearrangement procedure to move data of the selected at least one sub-region to a first memory space having continuous physical addresses.

Abstract: The invention introduces an apparatus for controlling different types of storage units, at least including: an interface and a processing unit. The interface connects at least two types of storage units, which include at least a nonvolatile hybrid memory. The processing unit is configured to operably access data to the different types of storage units through the interface.