Abstract: A method for performing data access management of a memory device in predetermined communications architecture with aid of unbalanced table update size and associated apparatus are provided. The memory device may be arranged to receive a set of first commands, receive a set of first data with a first active block according to the set of first commands, and update a temporary physical-to-logical (P2L) address mapping table corresponding to the first active block, and determine a selected table update size among multiple predetermined table update sizes such as multiple table entry counts and update at least one logical-to-physical address mapping table according to a set of P2L table entries corresponding to the selected table update size in the temporary P2L address mapping table, where the table update size may be dynamically changed for enhancing overall performance.

Abstract: A bridge device includes a first controller and a second controller. The first controller includes a first transmission interface. The second controller includes a second transmission interface. The first transmission interface and the second transmission interface are flash memory interfaces. In a program mode, the first transmission interface receives a first command from the second transmission interface and obtains first transfer data from a bus in response to the first command. A value of the first command is optionally set to a first value or a second value. The first value indicates a memory command transfer operation in a first direction and the second value indicates a memory data transfer operation in the first direction. The first transmission interface processes the first transfer data according to the value of the first command to obtain a memory command or written data.

Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple memory blocks. The memory blocks includes one or more spare memory blocks that are not written with data and one or more predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller is coupled to the memory device and configured to access the memory device. The memory controller is configured to determine a setting value of a number of said one or more predetermined memory blocks according to a number of currently remaining spare memory block(s), a number of the predetermined memory block(s) that has/have been written with data among said one or more predetermined memory blocks and a predetermined threshold, and configure the number of the predetermined memory block(s) as the buffer according to the setting value.

Abstract: The invention relates to a method and an apparatus for executing Structural Query Language (SQL) instructions in a Solid-state Storage Device (SSD). The apparatus includes: a processing unit; and a database accelerator. The processing unit is arranged operably to obtain an SQL query from a host side. The database accelerator is arranged operably to parse the SQL query according an SQL syntax tree to generate a series of table tasks to execute; and during the execution of the table tasks, read tables from a flash module through the processing unit, generate intermediate tables and sub-tables based on the read tables, and perform an arithmetic computation, a logical computation or both on a specific field in one intermediate table to generate a final dataset. The processing unit is arranged operably to reply to the host side with the final dataset.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for executing host write commands.

Abstract: The invention introduces an apparatus and a method for expanding round keys during data encryption. The method includes: configuring a word-processing circuitry to operate in a first mode to calculate a first intermediate calculation result corresponding to an even-number round key according to a last double word of a 0th double word to a 7th double word in each even-number clock cycle starting from a 2nd clock cycle; and configuring the word-processing circuitry to operate in a second mode to calculate a second intermediate calculation result corresponding to an odd-number round key according to the last double word of the 0th double word to the 7th double word in each odd-number clock cycle starting from a 3rd clock cycle. In the first mode, a first data path is formed in the word-processing circuitry, which includes a word split circuitry, a rotate-word circuitry, a substitute-word circuitry, a round-constant circuitry and a word concatenation circuitry.

Abstract: A method for performing data access control of a memory device includes: receiving a plurality of host commands from a host device for performing data access upon a non-volatile (NV) memory according to the plurality of host commands, wherein the data access includes data reading; and performing a read optimization procedure for maintaining correctness of the data reading, for example: performing reading operation to obtain multiple channel values; performing compression operation to convert multiple first soft bits in any channel value into multiple second soft bits, to generate a compressed channel value for being buffered in volatile memory; reading multiple compressed channel values from the volatile memory; and utilizing a low-density parity-check (LDPC) code decoding engine circuit to perform LDPC code decoding according to the multiple compressed channel values, and utilizing an error recovery circuit to perform error recovery operation according to the multiple channel values, to generate error-free d

Abstract: A method for performing access management of a memory device in a predetermined communications architecture with aid of automatic parameter setting and associated apparatus are provided. The method includes: utilizing the memory controller to set at least one write booster static parameter of a write booster function of the memory device; utilizing the memory controller to perform device initialization corresponding to at least one initialization phase of the memory device; and after completing the device initialization corresponding to the at least one initialization phase, performing at least one adaptive flag-setting operation, for setting at least one write booster flag among a plurality of write booster flags of the write booster function, wherein the at least one write booster flag includes a first write booster flag acting as a write booster switch. The adaptive flag-setting operation includes setting the first write booster flag to enable the write booster function by default.

Abstract: A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.

Abstract: A flash memory controller is used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface and includes an input/output (I/O) circuit and a processor. The I/O circuit is coupled to the flash memory device through the specific communication interface, and used for sending commands and data between the flash memory device and the processor. The processor is used for controlling the I/O circuit sending a specific boundary check command signal or a specific boundary check set-feature signal via the specific communication interface to the flash memory device, to make the flash memory device read out more page data of multiple page units from a specific block in the memory cell array and to make the flash memory device determine whether the multiple page units are empty pages.

Abstract: A video wall system with software running on a host computer and a video wall control device is shown. Using the software, the user inputs the size of each screen of a video wall and, accordingly, the delay time for each row of screens of the video wall is calculated. The video wall control device couples the host computer to the screens. The video wall control device outputs a plurality of split videos to the different screens through separated output ports, and drives each row of screens to display according to the delay time calculated for the row of screens.

Abstract: The present invention provides a host device coupled to a memory device, wherein the host device includes a processor, and the processor is configured to perform the steps of: (a) configuring a plurality of transport request descriptors in a memory; (b) writing a plurality of command descriptors into the memory in sequence, wherein a number of the command descriptors is greater than a number of the transport request descriptors; (c) selecting a transport request descriptor from the transport request descriptors sequentially and repeatedly, and determining a command descriptor sequentially without repetition; (d) modifying the transport request descriptor according to the command descriptor; (e) reading the transport request descriptor to send a command in the command descriptor to the memory device; and (f) determining whether a last command descriptor has been processed, if not, going back to step (c), and executing steps (c)-(f) in sequence.

Abstract: A data storage device includes a memory device and a memory controller. In response to a write command received from a host device, the memory controller performs a write operation to write predetermined data into the memory device. In the write operation, the memory controller selects one from multiple superblocks as a first target superblock of the write operation and sequentially writes the portions of the predetermined data into the pages of the first target superblock in a cyclic manner among memory dies according to an order of plane indices. Each memory die includes at least a first plane and a second plane. In the write operation corresponding to the predetermined data, corresponding write operations performed on a first page on the first plane of all memory dies are earlier than corresponding write operations performed on a first page on the second plane of all memory dies.

Abstract: A method for performing data access control of a memory device and associated apparatus are provided. The method may include: receiving a plurality of host commands from a host device, for performing data access including data reading on the NV memory according to the plurality of host commands; and performing a reading parameter learning procedure to generate predicted data of a predicted reading voltage parameter offset regarding adjustment of a reading voltage parameter, for maintaining correctness of the data reading, for example: scanning for a best value, and adding latest information comprising the best value into a data set among one or more data sets in at least one reading-voltage control database; performing local linear regression according to the data set to update a reading voltage prediction function corresponding to a reading voltage prediction model; and generating or updating the predicted data according to the reading voltage prediction function.

Abstract: A method of a flash memory device to be used in a storage device and coupled to a flash memory controller of the storage device through a specific communication interface, the flash memory device comprising an input/output (I/O) control circuit, a command register, an address register, a memory cell array at least having a first plane and a second plane which is different from the first plane, at least one address decoder, and a control circuit having a specific buffer, and the method comprises: buffering command information of a command signal, sent from the flash memory controller and transmitted through the I/O control circuit, into the command register; buffering address information of the command signal, sent from the flash memory controller and transmitted through the I/O control circuit, into the address register; and controlling the specific buffer storing a transmission history information of the specific communication interface.

Abstract: An input/output (I/O) interface circuit, disposed within a flash memory controller and to be coupled to a flash memory externally coupled to the flash memory controller through an I/O signal port of the flash memory controller, includes a transmission and on-die termination circuit operating as either an output driving stage circuit or an input on-die termination stage circuit. The transmission and on-die termination circuit operates as the output driving stage circuit to transfer and drive a transmission signal, sent from the processor circuit of the flash memory controller, to the flash memory through the I/O signal port. The transmission and on-die termination circuit operates as the input on-die termination stage circuit for generating and providing a matching termination resistance for the I/O signal port.

Abstract: A flash memory controller and a data programming method are provided. The flash memory controller includes a control logic circuit and a processor. The control logic circuit is coupled to a first chip-enable-signal controlled area of a flash memory through a channel to transmit data and commands. The processor controls the control logic circuit to transmit a first command and a second command to the first chip-enable-signal controlled area through the channel. The first command is configured to instruct the first chip-enable-signal controlled area to write stored data and read operating temperature information. In response to the transmission of the second command, the processor controls the control logic circuit to receive the operating temperature information from the first chip-enable-signal controlled area.

Abstract: A control method of a memory device includes: updating a wear leveling related data temporarily stored in a buffer memory; obtaining multiple parameters; determining a write frequency according to the multiple parameters; and copying the wear leveling related data from the buffer memory to a flash memory module included in the memory device according to the write frequency.

Abstract: A method for performing data access control for a host device includes: receiving a plurality of host commands from the host device, for performing data access on at least one medium according to the plurality of host commands, wherein the data access includes data receiving; and performing a data access optimization procedure for maintaining correctness of the data receiving that includes: performing the data receiving on the at least one medium to obtain at least one code word; performing multiple first low-density parity-check (LDPC) code decoding operations regarding multiple column segments, where a portion of column segments are abnormal column segments corresponding to puncture variable nodes; finding at least one column segment satisfying predetermined selection condition, to perform at least one second LDPC code decoding operation regarding the at least one column segment; performing multiple third LDPC code decoding operations regarding the multiple column segments; and returning error-free data.

Abstract: The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, the flash memory module comprises a plurality of blocks, and the control method comprising: receiving a settling command from a host device; in response to the settling command, configuring at least one portion of the flash memory module as a zoned namespace, wherein the zoned namespace logically comprises a plurality of zones; generating parameter information according to a configuration of the zoned namespace; and transmitting the parameter information to the host device, for the host device uses the parameter information to set the zone.