Abstract: The present invention provides a host device coupled to a memory device, wherein the host device includes a processor, and the processor is configured to perform the steps of: (a) configuring a plurality of transport request descriptors in a memory; (b) writing a plurality of command descriptors into the memory in sequence, wherein a number of the command descriptors is greater than a number of the transport request descriptors; (c) selecting a transport request descriptor from the transport request descriptors sequentially and repeatedly, and determining a command descriptor sequentially without repetition; (d) modifying the transport request descriptor according to the command descriptor; (e) reading the transport request descriptor to send a command in the command descriptor to the memory device; and (f) determining whether a last command descriptor has been processed, if not, going back to step (c), and executing steps (c)-(f) in sequence.

Abstract: A data storage device includes a memory device and a memory controller. In response to a write command received from a host device, the memory controller performs a write operation to write predetermined data into the memory device. In the write operation, the memory controller selects one from multiple superblocks as a first target superblock of the write operation and sequentially writes the portions of the predetermined data into the pages of the first target superblock in a cyclic manner among memory dies according to an order of plane indices. Each memory die includes at least a first plane and a second plane. In the write operation corresponding to the predetermined data, corresponding write operations performed on a first page on the first plane of all memory dies are earlier than corresponding write operations performed on a first page on the second plane of all memory dies.

Abstract: An input/output (I/O) interface circuit, disposed within a flash memory controller and to be coupled to a flash memory externally coupled to the flash memory controller through an I/O signal port of the flash memory controller, includes a transmission and on-die termination circuit operating as either an output driving stage circuit or an input on-die termination stage circuit. The transmission and on-die termination circuit operates as the output driving stage circuit to transfer and drive a transmission signal, sent from the processor circuit of the flash memory controller, to the flash memory through the I/O signal port. The transmission and on-die termination circuit operates as the input on-die termination stage circuit for generating and providing a matching termination resistance for the I/O signal port.

Abstract: A method of a flash memory device to be used in a storage device and coupled to a flash memory controller of the storage device through a specific communication interface, the flash memory device comprising an input/output (I/O) control circuit, a command register, an address register, a memory cell array at least having a first plane and a second plane which is different from the first plane, at least one address decoder, and a control circuit having a specific buffer, and the method comprises: buffering command information of a command signal, sent from the flash memory controller and transmitted through the I/O control circuit, into the command register; buffering address information of the command signal, sent from the flash memory controller and transmitted through the I/O control circuit, into the address register; and controlling the specific buffer storing a transmission history information of the specific communication interface.

Abstract: A method for performing data access control of a memory device and associated apparatus are provided. The method may include: receiving a plurality of host commands from a host device, for performing data access including data reading on the NV memory according to the plurality of host commands; and performing a reading parameter learning procedure to generate predicted data of a predicted reading voltage parameter offset regarding adjustment of a reading voltage parameter, for maintaining correctness of the data reading, for example: scanning for a best value, and adding latest information comprising the best value into a data set among one or more data sets in at least one reading-voltage control database; performing local linear regression according to the data set to update a reading voltage prediction function corresponding to a reading voltage prediction model; and generating or updating the predicted data according to the reading voltage prediction function.

Abstract: A flash memory controller and a data programming method are provided. The flash memory controller includes a control logic circuit and a processor. The control logic circuit is coupled to a first chip-enable-signal controlled area of a flash memory through a channel to transmit data and commands. The processor controls the control logic circuit to transmit a first command and a second command to the first chip-enable-signal controlled area through the channel. The first command is configured to instruct the first chip-enable-signal controlled area to write stored data and read operating temperature information. In response to the transmission of the second command, the processor controls the control logic circuit to receive the operating temperature information from the first chip-enable-signal controlled area.

Abstract: A control method of a memory device includes: updating a wear leveling related data temporarily stored in a buffer memory; obtaining multiple parameters; determining a write frequency according to the multiple parameters; and copying the wear leveling related data from the buffer memory to a flash memory module included in the memory device according to the write frequency.

Abstract: A method for performing data access control for a host device includes: receiving a plurality of host commands from the host device, for performing data access on at least one medium according to the plurality of host commands, wherein the data access includes data receiving; and performing a data access optimization procedure for maintaining correctness of the data receiving that includes: performing the data receiving on the at least one medium to obtain at least one code word; performing multiple first low-density parity-check (LDPC) code decoding operations regarding multiple column segments, where a portion of column segments are abnormal column segments corresponding to puncture variable nodes; finding at least one column segment satisfying predetermined selection condition, to perform at least one second LDPC code decoding operation regarding the at least one column segment; performing multiple third LDPC code decoding operations regarding the multiple column segments; and returning error-free data.

Abstract: An electronic device includes a functional circuit, a test mode circuit, and a verification circuit. The verification circuit generates and outputs the test waveform signals into the test mode circuit based on a clock signal provided from the test mode circuit, receives test result waveform signals from the test mode circuit when at least one test operation corresponding to the test pattern signal is performed, and compares the test result waveform signals with target result waveform signals to generate and output a failure result signal into the test mode circuit; the failure result signal is used to indicate whether at least one test bit failure occurs.

Abstract: The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, the flash memory module comprises a plurality of blocks, and the control method comprising: receiving a settling command from a host device; in response to the settling command, configuring at least one portion of the flash memory module as a zoned namespace, wherein the zoned namespace logically comprises a plurality of zones; generating parameter information according to a configuration of the zoned namespace; and transmitting the parameter information to the host device, for the host device uses the parameter information to set the zone.

Abstract: A technique for signal deskew at the non-volatile memory side. The non-volatile memory includes a plurality of dies and a signal timing adjustment circuit. The dies are grouped into storage zones. A controller is coupled to the non-volatile memory through a plurality of data lines. Through the data lines, the controller issues a plurality of commands to provide zone delay parameters to the non-volatile memory to drive the signal timing adjustment circuit at the non-volatile memory side to separately adjust data-line timing of the different storage zones.

Abstract: A method of handling trim commands in a flash memory is provided. The method comprises: receiving a trim command; modifying logical-to-physical (L2P) address mapping entries of a L2P address mapping table according to the trim command; and storing trim information of the trim command into one of data blocks of the flash memory after modifying the L2P address mapping entries according to the trim command.

Abstract: A method for performing data access control of a memory device and associated apparatus are provided.

Abstract: A method for performing data access control of a memory device and associated apparatus are provided. The method may include: receiving a plurality of host commands from a host device, for performing data access including data reading on the NV memory according to the plurality of host commands; and performing a reading parameter learning procedure to generate predicted data of a predicted reading voltage parameter offset regarding adjustment of a reading voltage parameter, for maintaining correctness of the data reading, for example: scanning for a best value, and adding latest information comprising the best value into a data set among one or more data sets in at least one reading-voltage control database; performing local linear regression according to the data set to update a reading voltage prediction function corresponding to a reading voltage prediction model; and generating or updating the predicted data according to the reading voltage prediction function.

Abstract: A method for calibrating a characteristic value of a signal processing device comprised in SerDes inside of an interface circuit of a memory controller includes: monitoring a current of a voltage of a test element to generate a process detection result by a monitor and calibration module; monitoring an environment temperature to generate a temperature monitored result by the monitor and calibration module; selecting a reference value subset from multiple reference value subsets as a preferred reference value subset for a calibration operation based on the process detection result and the temperature monitored result; and performing the calibration operation on the signal processing device by at least one calibration circuit of the monitor and calibration module according to the preferred reference value subset to adjust the characteristic value of the signal processing device.

Abstract: The present invention provides a method for controlling a flash memory module. The method includes the steps of: after the flash memory module is powered on, determining whether the flash memory module encountered an abnormal power failure before the flash memory module is powered on; if the flash memory module encounters the abnormal power failure before the flash memory module is powered on, determining a last super block written by the flash memory module before powering on, where the super block includes multiple first blocks; determining a last rewritten page of the super block; determining a check range of the super block according to the last written page of the super block; determining a data weak region of the super block by reading the pages of the check range; and moving data in the weak data region to other regions of the super block or to another super block.

Abstract: A control method of a memory device includes: reading and decoding first data of a first chunk, wherein the first chunk is located in a first data page of a super data page, and the super data page includes multiple data pages respectively located in multiple data planes; in response to the first chunk failing to be decoded, obtaining data of multiple corresponding chunks of the first chunk, wherein the multiple corresponding chunks are located in other data pages of the super data page; and in response to all of the data in the multiple corresponding chunks not being successfully decoded, determining whether to give up the decoding operation of the first chunk according to a symptom weight of the first chunk and at least one symptom weight of at least one corresponding chunk.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the method includes the steps of: using a first set of threshold voltages, a positively adjusted first set of threshold voltages and a negatively adjusted first set of threshold voltages to read a first logical page of a physical page of the flash memory module to obtain first readout information, second readout information and third readout information, respectively; decoding the first readout information, the second readout information and the third readout information to generate decoded data of the first logical page; and generating a LLR mapping table according to the decode data of the first logical page, the first readout information, the second readout information and the third readout information, for use when reading and decoding other logical pages.

Abstract: A flash memory controller, to be coupled between a host device and a flash memory module, includes an error correction code (ECC) circuit. The ECC circuit performs a wordline-dimensional ECC operation upon specific data, sent from the host device to form a super block stored within the flash memory module, to generate wordline-dimensional parity data and performs a finger-dimensional ECC operation upon the specific data generate finger-dimensional parity data. The ECC circuit corrects an error of the superblock by using the wordline-dimensional parity data and the finger-dimensional parity data so as to obtain correct data content of the specific data.

Abstract: A flash memory controller, to be coupled between a host and a flash memory module, includes an error correction code (ECC) circuit. The ECC circuit performs a wordline-dimensional ECC operation upon specific data, sent from the host to form a super block stored within the flash memory module, to generate wordline-dimensional check code data and performs a finger-dimensional ECC operation upon the specific data generate finger-dimensional check code data. The ECC circuit corrects an error of the superblock by using the wordline-dimensional check code data and the finger-dimensional check code data so as to obtain correct data content of the specific data.