Abstract: A solution for deteriorated non-volatile memory is shown. When a controller determines that raw data read from the non-volatile memory is undesirable data, the controller performs safety moving of valid data of an erasure unit that contains the raw data to safely move the valid data of the erasure unit, wherein the erasure unit is a high-risk block, and the raw data in the non-volatile memory is regarded as being in a deteriorated physical address. Prior to being moved in the safety moving, the raw data is changed so that it is different from the undesirable data. In an exemplary embodiment, the undesirable data is all-1's data or all-0's data.

Abstract: A method of a flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface includes: using a set-feature signal, which carries a set-feature command, a macro execution feature address, and corresponding macro execution parameter information, as a macro execution signal and transmitting the macro execution signal to the flash memory device to make the flash memory device execute multiple set-feature operations respectively having unique information defined by the corresponding macro execution parameter information carried in the macro execution signal.

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: A data storage device, and an error tolerance selecting method thereof which includes: writing data to data blocks of the data storage device; reading written data of the data blocks as read data; comparing the read data and the written data of each data column in the data blocks, and calculating a number of error bits in each chunk including a plurality of data columns accordingly; calculating a difference value between the number of error bits in the chunk and a first threshold value to store the difference value in an error tolerance list; and selecting a largest difference value in the error tolerance list as an error tolerance.

Abstract: A method for performing access management of a memory device with aid of serial number assignment timing control and associated apparatus are provided. The method includes: managing a plurality of spare blocks with a spare pool; popping a first block from the spare pool to be a host data block, and performing first subsequent operations, wherein the host data block is arranged to receive data from a host device, and serial number assignment of the host data block corresponds to a timing of fully programing the host data block; and popping a second block from the spare pool to be a garbage collection (GC) destination block, and performing second subsequent operations, wherein the GC destination block is arranged to receive data from a GC source block during a GC procedure, and serial number assignment of the GC destination block corresponds to a timing of starting using the GC destination block.

Abstract: A method, for calibrating signal processing devices in an interface circuit coupled to a host device, comprises: negotiating with the host device in a link up process about an operation mode for the interface circuit to operate in a calibration procedure; and calibrating a characteristic value of a first signal processing device and a characteristic value of a second signal processing device in the calibration procedure. The first signal processing device is disposed on a receiving signal processing path and configured to process a received signal and the second signal processing device is disposed on a transmitting signal processing path and configured to process a transmitting signal, and the interface circuit is configured to operate based on the operation mode in the calibration procedure.

Abstract: A method for performing communications specification version control of a memory device in predetermined communications architecture with aid of compatibility management, associated apparatus and computer-readable medium are provided.

Abstract: A method for performing automatic setting control of a memory device in predetermined communications architecture with aid of auxiliary setting management and associated apparatus are provided.

Abstract: A memory controller for use in a data storage device is provided. A low-density parity check (LDPC) process performed by the memory controller includes an initial phase, a decoding phase, and an output phase. The memory controller includes a variable-node circuit and a check-node circuit. During the initial phase, the variable-node circuit performs the following steps: obtaining a channel value, that is read from a flash memory, from a channel-value memory; transmitting the channel value to the check-node circuit to calculate a syndrome; and in response to the syndrome not being 0, setting a value of a register corresponding to each entry of a plurality of entries in a variable-node memory, and entering the decoding phase.

Abstract: A method for performing data fragmentation reduction control of a memory device in a predetermined communications architecture with aid of fragmentation information detection, associated apparatus and computer-readable medium are provided.

Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.

Abstract: A method for performing link management of a memory device in predetermined communications architecture with aid of handshaking phase transition control and associated apparatus are provided. The method may include: utilizing at least one upper layer controller of a transmission interface circuit to turn on a physical layer (PHY) circuit of the transmission interface circuit, for starting establishing a link between a host device and the memory device; before entering a first handshaking phase, utilizing the PHY circuit to receive any first incoming data sent from the host device to determine whether the any first incoming data indicates that the host device is in a corresponding first handshaking phase; and in response to the any first incoming data indicating that the host device is in the corresponding first handshaking phase, utilizing the PHY circuit to send first outgoing data that is equal to first predetermined data to the host device.

Abstract: A memory controller coupled to a memory device for accessing the memory device and includes a Universal Asynchronous Receiver/Transmitter (UART) and a microprocessor. The microprocessor is coupled to the UART and configured to control access operations of the memory device. The microprocessor is configured to perform an interrupt service routine in response to an interrupt. When performing the interrupt service routine, the microprocessor is configured to determine whether a predetermined signal has been received by a specific pin and when determining that the predetermined signal has been received by the specific pin, the microprocessor is configured to output a debug message through a transmitting terminal of the UART.

Abstract: A method for performing data retention management of a memory device with aid of pre-shutdown control and associated apparatus are provided. The method may include: receiving a predetermined host command from a host device; in response to the predetermined host command, performing a re-programming procedure on the NV memory, for enhancing data storage reliability of the memory device, for example, reading stored data from at least one source location within the at least one NV memory element to prepare re-programming data according to the stored data, and programming the re-programming data into at least one destination location within the at least one NV memory element to be replacement of the stored data; and in response to the re-programming procedure being completed, sending completion information of the predetermined host command to the host device, to allow the host device to trigger the shutdown of the memory device.

Abstract: A method for performing data management of a memory device with aid of targeted protection control and associated apparatus are provided. The method may include: receiving a first host command from a host device; sending a first operating command to a non-volatile (NV) memory to read first stored data from a first location within the NV memory; monitoring a read count of the first location to determine whether the read count of the first location reaches a read count threshold; monitoring at least one error bit count of other stored data of at least one other location within the NV memory to determine whether the at least one error bit count reaches an error bit count threshold; and starting a targeted protection procedure to process second stored data, for preventing the second stored data from being damaged by at least one reading behavior of the host device.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for decoding a Low-Density Parity-Check (LDPC) code. The method, which is performed by a processing unit in an LDPC decoder, includes the following steps: determining whether a bit flipping algorithm when decoding a codeword enters a trapping state after an observation period during which a sequential selection strategy is used; and modifying a scheduling strategy to a non-sequential selection strategy and performing the bit flipping algorithm on the codeword under the non-sequential selection strategy when the bit flipping algorithm enters the trapping state. The codeword is divided into chunks in fixed-length and the sequential selection strategy indicates sequentially selecting the chunks in the codeword, so that the bit flipping algorithm is performed on one selected chunk only each time.

Abstract: A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.

Abstract: A control method for a multi-channel non-volatile memory is shown. When reading a read target on the non-volatile memory, the controller increases the read count of the monitored unit to which the read target belongs and, based on the read count, determines whether to move data of the monitored unit covering the read target to a safe space to deal with reading interference. The monitored unit is smaller than a cross-channel management unit in read-count group. The controller accesses a parallel accessing space of the non-volatile memory in parallel through all of the channels, and allocates the parallel accessing space based on the cross-channel management unit.