Abstract: A method for managing a memory apparatus including a plurality of physical blocks, and a volatile memory includes: obtaining a first host address and first data, and obtaining a second host address and second data; linking the first host address and second host address to a first page and second page of the physical block, and storing the first data and second data into the physical block; building a valid/invalid page count table according to a valid/invalid page count of the physical block; building a valid page position table according to the valid/invalid page count table, and storing the valid/invalid page count table in the volatile memory; and when a valid/invalid page count of the physical block indicates the physical block should be erased, using the valid page position table to move valid pages of the physical block to another physical block.

Abstract: A data storage device includes at least one signal processing circuit to perform an error recovery procedure when an error has occurred in the data storage device. When performing the error recovery procedure, the signal processing circuit determines which type of line reset is to be performed according to a device identifier. When the device identifier satisfies a predetermined condition, the signal processing circuit performs an operation of periodic line reset to repeatedly transmit a line reset signal to the peer device in a predetermined period until the predetermined period expires or another line reset signal representing an acknowledgment of the line reset signal is received from the peer device; and when the device identifier does not satisfy the predetermined condition, the signal processing circuit performs an operation of one-shot line reset to transmit the line reset signal to the peer device for only one time.

Abstract: A data storage device includes a memory device and a memory controller. The memory device has a corresponding total storage capacity and includes multiple memory blocks. The total storage capacity is set to a maximum storage capacity provided by the memory blocks by default. The memory blocks include one or more predetermined memory blocks configured as a buffer to receive data from a host device. The memory controller is coupled to the memory device to access the memory device. In response to setting of a maximum amount of write data, the memory controller determines a value of the total storage capacity according to the maximum amount of write data, and determines a number of said one or more predetermined memory blocks according to the value of the total storage capacity and the maximum storage capacity.

Abstract: A data storage device includes an interface circuit to process reception signals received from a peer device and transmission signals to be transmitted to the peer device. The interface circuit includes at least one signal processing circuit to perform an error recovery procedure when an error has occurred in the data storage device. When performing the error recovery procedure, the signal processing circuit performs an operation of periodic line reset to repeatedly transmit a line reset signal to the peer device within a predetermined period until the predetermined period expires or another line reset signal representing an acknowledgment of the line reset signal has been received from the peer device.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for executing host write commands.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for executing host write commands. The method performed by a processing unit includes: providing a sequential-write command queue (SCQ), a random-write command queue (RCQ) and a mark queue; receiving a host write command from a host side; and pushing a record into the mark queue and pushing the host write command into the SCQ or the RCQ according to a length of the first logical address range carried in the host write command when detecting that a first logical address range carried in the host write command conflicts with a second logical address range carried in at least one sequential write command and/or a third logical address range carried in at least one random write command, where the record indicates that a conflicting sequential write command and/or a conflicting random write command needs to be processed earlier than the host write command.

Abstract: The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the control method includes the steps of: receiving a settling command from a host device to configure a portion space of the flash memory module as a zoned namespace; receiving a write command from the host device to write data corresponding a first zone into a plurality of blocks of the flash memory module, wherein an access mode chose by the flash memory controller is determined based on a size of each zone and a size of each block.

Abstract: A method for performing data management of a memory device with aid of targeted protection control and associated apparatus are provided. The method may include: receiving a first host command from a host device; sending a first operating command to a non-volatile (NV) memory to read first stored data from a first location within the NV memory; monitoring a read count of the first location to determine whether the read count of the first location reaches a read count threshold; monitoring at least one error bit count of other stored data of at least one other location within the NV memory to determine whether the at least one error bit count reaches an error bit count threshold; and starting a targeted protection procedure to process second stored data, for preventing the second stored data from being damaged by at least one reading behavior of the host device.

Abstract: A method for performing a test upon a flash memory module includes: performing data writing upon a plurality of first blocks of a first group in the flash memory module; reading the plurality of first blocks of the first group to determine whether there is any abnormal block in the plurality of first blocks and generating a first test result; after the plurality of first blocks are read, performing data writing upon a plurality of second blocks of a second group in the flash memory module; and reading the plurality of second blocks of the second group to determine whether there is any abnormal block in the plurality of second blocks and generating a second test result.

Abstract: A method of managing operation commands for a flash memory includes: providing a first command queue for receiving and storing a plurality of normal operation commands; providing at least one word line read (IWLR) command queue for receiving and storing a plurality of IWLR operation commands; issuing a lock state command between each two consecutive IWLR operation commands to the at least one second command queue; determining a selected command queue from the first command queue and the at least one IWLR command queues according to the lock state command; and delivering an operation command from the selected command queue to the flash memory.

Abstract: A solution for deteriorated non-volatile memory is shown. When determining that raw data read from the non-volatile memory is undesirable data, the controller updates a deterioration table to record a deteriorated logical address of the raw data that is the undesirable data. In response to a read request that a host issues to read the non-volatile memory for data of the deteriorated logical address, the controller obtains the deteriorated logical address from the deterioration table and informs the host that deterioration has happened at the deteriorated logical address.

Abstract: A data storage device with flash memory. The controller receives a mode selection command from a host. In response to the mode selection command, the controller sends a ready-to-transfer message to the host, to further receive a data out message from the host that is sent by the host in response to the ready-to-transfer message. The ready-to-transfer message and the data out message are UFS protocol information unit (UPIU) messages. The data out message is arranged to rewrite a first mode page setting among a plurality of mode page settings of firmware stored in the flash memory. In response to the data out message, the controller determines whether the data out message will change mode parameters which cannot be rewritten in the first mode page setting, to adopt or refuse new mode parameters issued through the data out message for the first mode page setting.

Abstract: A flash memory controller is arranged to access a flash memory module, and includes a transmission interface circuit a buffer memory, and a microprocessor. The transmission interface circuit is coupled to a host device, wherein the transmission interface circuit includes a command processing circuit, and the command processing circuit is arranged to: receive a command from the host device; utilize multiple check items to check the command to generate at least one check result; and convert the command to generate a converted command of a specific format, wherein the converted command comprises an error state field for recording the at least one check result. The buffer memory is arranged to store the converted command. The microprocessor is arranged to read the converted command from the buffer memory, and access the flash memory module according to the converted command.

Abstract: A flash memory controller is arranged to access a flash memory module, and includes a transmission interface circuit, a buffer memory, and a microprocessor. The transmission interface circuit is coupled to a host device, wherein the transmission interface circuit includes a command processing circuit, the command processing circuit is arranged to receive a command from the host device and convert the command to generate a converted command of a specific format, the command supports multiple formats, and the specific format is different from the multiple formats. The buffer memory is arranged to store the converted command. The microprocessor is arranged to read the converted command from the buffer memory, and access the flash memory module according to the converted command.

Abstract: A control method of a memory device includes: controlling a flash memory controller to transmit a command to a flash memory module; determining whether the flash memory controller is in an idle state; in response to the flash memory controller being in the idle state, determining whether an idle time of the idle state exceeds a threshold value, wherein the threshold value is less than a time required for the flash memory module to complete executing a write command or an erase command; and in response to the idle time exceeding the threshold value, controlling the flash memory controller to enter a power saving mode to turn off a part of components in the flash memory controller.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for executing host commands. The method performed by a processing unit includes: setting a first start register and a first end register to store a first logical address range from a first start logical address to a first end logical address for an execution of a host command; providing a sequential update queue including multiple entries; setting an activation register to drive a search engine; checking values of a matching register and a resulting address register of the search engine to determine whether a whole or a portion of data of the first logical address range is temporarily stored in the RAM after a time period; and if so, manipulating the whole or a portion of data of the first logical address range that is temporarily stored in the RAM.

Abstract: The invention relates to an apparatus for searching for logical address ranges of host commands. The first comparator outputs logic “0” to the NOR gate when a first end logical address is not smaller than a second start logical address. The second comparator outputs logic “0” to the NOR gate when a second end logical address is not smaller than a first start logical address. The NOR gate outputs logic “1” to a matching register and an output circuitry when receiving logic “0” from both the first and the second comparators. The output circuitry outputs a memory address of a random access memory (RAM) storing a second logical address range from the second start logical address to the second end logical address to a resulting address register when receiving logic “1” from the NOR gate.

Abstract: A memory controller coupled to a memory device and configured to control access operations of the memory device includes a data protection engine and a microprocessor. The data protection engine is configured to generate protection information according to data received from a host device. The microprocessor is configured to detect a status of the memory device in response to one or more write operations for writing the data to the memory device, determine whether a portion of the data has to be excluded when generating the protection information corresponding to the data according to the status and accordingly generate a determination result, and store the protection information and the determination result together in the memory device. The determination result indicates which portion of the data is utilized to generate the protection information.

Abstract: A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information encoding and decoding are provided. The method may include: encoding internal information of the memory device and sending encoded result thereof to a host device, to allow the host device to store the encoded result in a memory within the host device as host-owned encoded device side table information at the host device; generating and storing multiple entries of address mapping control table into a RAM as at least one portion of device side table information at the memory device; decoding partial information of the host-owned encoded device side table information, performing checking operation on decoded result thereof, and selectively using the decoded result to determine physical address associated with logical address; and reading data from the NV memory according to the physical address.

Abstract: A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information encoding and decoding are provided. The method may include: encoding internal information of the memory device and sending encoded result thereof to a host device, to allow the host device to store the encoded result in a memory within the host device as host-owned encoded device side table information at the host device; generating and storing multiple entries of address mapping control table into a RAM as at least one portion of device side table information at the memory device; decoding partial information of the host-owned encoded device side table information, performing checking operation on decoded result thereof, and selectively using the decoded result to determine physical address associated with logical address; and reading data from the NV memory according to the physical address.