Abstract: The invention introduces a method for performing data writes into a flash memory, at least including the steps: determining whether at least one host write command that requires to process immediately is presented in a submission queue (SQ) before performing a portion of a Host-Flash mapping (H2F) table update or a GC process; and executing the host write command that requires to process immediately in a batch and then performing the portion of the H2F table update or the GC process when the determination is positive.

Abstract: A bridge control chip includes a first interface, a second interface, and a processor, wherein the first interface is coupled to a host device, the second interface is coupled to a memory device, and the memory device is a flash memory device. The processor is arranged to execute commands in a queue in sequence, to transmit the commands in the queue to the memory device through the second interface in sequence, wherein when the processor receives one or more received commands from the host device, the processor sorts the one or more received commands and commands which are currently and temporarily stored in the queue according to a distance between a logical address of each of the one or more received commands and a logical address of a current command in the queue that is currently executed by the processor.

Abstract: The invention introduces a method for scheduling and executing host data-update commands. A first queue and a second queue are provided. The first queue includes first host data-update commands each including a first logical address. The second queue includes second host data-update commands each including a second logical address. A third host data-update command including a third logical address is generated and is labeled as a first type of host data-update command according to a host command received from a host side. All the first host data-update commands of the first queue are popped out and executed in response that the third logical address is the same as any first logical address. All the second host data-update commands of the second queue are popped out and executed in response that the third logical address is the same as any second logical address.

Abstract: The invention introduces a method for scheduling and executing host data-update commands. A first queue and a second queue are provided. The first queue includes first host data-update commands each including a first logical address. The second queue includes second host data-update commands each including a second logical address. A third host data-update command including a third logical address is generated and is labeled as a first type of host data-update command according to a host command received from a host side. A redundant first logical address is removed from a matched one of the first host data-update commands in response that the third logical address is the same as any first logical address. A redundant second logical address is removed from a matched one of the second host data-update commands in response that the third logical address is the same as any second logical address.

Abstract: A method of a storage device controller includes: using an interface circuit for receiving and storing different write address information of different write command signals sent from a host device, the different write address information being out of sequence; and, using multiple processor cores to rearrange the different write address information in sequence and then write data into at least one storage zone according to the different write address information rearranged in sequence.

Abstract: A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information encoding and decoding are provided. The method may include: encoding internal information of the memory device and sending encoded result thereof to a host device, to allow the host device to store the encoded result in a memory within the host device as host-owned encoded device side table information at the host device; generating and storing multiple entries of address mapping control table into a RAM as at least one portion of device side table information at the memory device; decoding partial information of the host-owned encoded device side table information, performing checking operation on decoded result thereof, and selectively using the decoded result to determine physical address associated with logical address; and reading data from the NV memory according to the physical address.

Abstract: A method of a flash memory controller includes: controlling an I/O circuit using a set-feature signal, which carries a set-feature command, feature address, and parameter information, and transmitting the set-feature signal to a flash memory device; the feature address corresponds to a valid data portion or a dummy data portion following the valid data portion, and both the valid data portion and dummy data portion are comprised in a full page data which is to be written into a physical page unit of the flash memory device or to be read out from the physical page unit; the corresponding parameter information is used to record the valid data portion's column address and data length, the dummy data portion's column address and data length, the dummy data portion's column address and the valid data portion's, or the dummy data portion's data length and the valid data portion's data length.

Abstract: A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information encoding and decoding are provided. The method may include: encoding internal information of the memory device and sending encoded result thereof to a host device, to allow the host device to store the encoded result in a memory within the host device as host-owned encoded device side table information at the host device; generating and storing multiple entries of address mapping control table into a RAM as at least one portion of device side table information at the memory device; decoding partial information of the host-owned encoded device side table information, performing checking operation on decoded result thereof, and selectively using the decoded result to determine physical address associated with logical address; and reading data from the NV memory according to the physical address.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the method includes the steps of: writing data into a plurality of pages of a specific block, and establishes or updates a F2H mapping table based on physical addresses of the plurality of pages and logical addresses of the data; using the F2H mapping table to update a H2F mapping table; initializing a flush-bitmap, wherein the flush-bitmap records a plurality of flush bits corresponding to the physical addresses of the plurality of pages, respectively; receiving a trim command from a host device, wherein the trim command asks to mark at least one of the logical addresses of the data as invalid; updating the H2F mapping data according to the trim command; updating the flush-bitmap according to the trim command; and writing the updated H2F mapping table and the updated flush-bitmap into the flash memory module.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller uses a first predetermined memory block as a buffer to receive data from a host device. In response to a write command received from the host device, the memory controller determines a sub-region corresponding to the write command, determines whether the sub-region is a system data sub-region and accordingly determines whether to use a second predetermined memory block as another buffer to receive data from the host device. When the memory controller determines that the sub-region corresponding to the write command is a system data sub-region, the memory controller writes the data into the second predetermined memory block. When the memory controller determines that the sub-region corresponding to the write command is not a system data sub-region, the memory controller writes the data into the first predetermined memory block.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller uses a first predetermined memory block as a buffer to receive data from a host device. In response to a write command received from the host device, the memory controller determines a sub-region corresponding to the write command, determines whether the sub-region is a hot-write sub-region according to a write count corresponding to the sub-region and accordingly determines whether to use a second predetermined memory block as another buffer to receive data from the host device. When the memory controller determines that the sub-region corresponding to the write command is a hot-write sub-region, the memory controller writes the data into the second predetermined memory block. When the memory controller determines that the sub-region is not a hot-write sub-region, the memory controller writes the data into the first predetermined memory block.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller maintains a write count for each sub-region of the memory device. When the memory controller has selected one or more sub-regions to perform a data rearrangement procedure, the memory controller further determines whether a selected sub-region is a hot-write sub-region according to the write count corresponding to the selected sub-region. When the memory controller determines that the selected sub-region is not a hot-write sub-region, the memory controller performs the data rearrangement procedure on the selected sub-region to move data corresponding to logical addresses belonging to the selected sub-region to a memory space of the memory device having continuous physical addresses. When the memory controller determines that the selected sub-region is a hot-write sub-region, the memory controller does not perform the data rearrangement procedure on the selected sub-region.

Abstract: A data storage device includes a memory device and a memory controller. When a sub-region of the memory device is selected based on a predetermined rule to perform a data rearrangement procedure, the memory controller determines whether the selected sub-region is a system data sub-region. When determining that the selected sub-region is not a system data sub-region, the memory controller performs the data rearrangement procedure on the selected sub-region to move data corresponding to logical addresses belonging to the selected sub-region to a memory space of the memory device having continuous physical addresses, and when determining that the selected sub-region is a system data sub-region, the memory controller does not perform the data rearrangement procedure on the selected sub-region.

Abstract: A method for performing memory access of a Flash cell of a Flash memory includes: performing a series of sensing operations respectively corresponding to a plurality of sensing voltages, wherein a sensing voltage of a specific sensing operation of the series of sensing operations has a sensing voltage determined according to a result of an initial sensing operation of the series of sensing operations; determining a threshold voltage of the Flash cell according to at least a digital value generated by the series of sensing operations; and using the determined threshold voltage to perform soft decoding of the Flash cell.

Abstract: A method for accessing a flash memory module includes: determining a type of data to be written into the flash memory module; selecting a specific encoding/decoding setting from a plurality of sets of encoding/decoding settings at least according to the type of data, wherein the plurality of sets of encoding/decoding settings correspond to different data lengths, respectively; utilizing the specific encoding/decoding setting to encode the data to generate encoded data; and writing the encoded data into a block of the flash memory module.

Abstract: A method for accessing a flash memory module includes: selecting a block in the flash memory module; selecting a specific encoding/decoding setting from a plurality of sets of encoding/decoding settings at least according to an erase count of the block, wherein the plurality of sets of encoding/decoding settings include different error correction code (ECC) lengths, respectively; utilizing the specific encoding/decoding setting to encode a data to generate an encoded data; and writing the encoded data into the block.

Abstract: A flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller into a simplified command sequence so as to reduce the waiting time period of the command transmission and improve the performance of flash memory.

Abstract: The invention relates to an apparatus and a system for debugging a solid-state disk (SSD) device. The apparatus includes a Joint Test Action Group (JTAG) add-on board; and a Raspberry Pi. The Raspberry Pi includes a General-Purpose Input/Output (GPIO) interface (I/F), coupled to the JTAG add-on board; and a processing unit, coupled to the GPIO I/F. The processing unit is arranged operably to: simulate to issue a plurality of JTAG command through the GPIO I/F to the SSD device for dumping data generated by the SSD device during operation from the SSD device.

Abstract: For an encoder for use in a flash memory controller, partial parity blocks generated in the encoder are divided into two parts for further operations, wherein a number of partial parity block(s) of the first part generated earlier is less than a number of partial parity block(s) of the second part. The encoder can reduce the hardware required for the circulant convolution calculation in the encoder, and has high efficiency. In addition, by converting a parity-check matrix to generate an isomorphic matrix, some components in the encoder and the decoder can be further omitted, so as to further reduce the manufacturing cost.

Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.