Abstract: A method of a flash memory controller coupled between a flash memory and an electronic device is provided. The flash memory has a plurality of blocks each having a plurality of pages. The method includes: detecting whether a data unit is formed by a repeated pattern, the data unit being transmitted from the electronic device and to be written into the flash memory or the data unit being read from the flash memory; and making a record of the repeated pattern at a field of the specific table if determining that the data unit is formed by the repeated pattern.

Abstract: A storage apparatus managing method, applied to a storage apparatus connected to a portable electronic apparatus, includes: (a) receiving authentication information via the portable electronic apparatus or the storage apparatus; (b) transmitting at least one confirmation command to a control module via a storage management program in the portable electronic apparatus, wherein the confirmation command is arranged to confirm whether the control module is in a ready state; (c) controlling the portable electronic apparatus to be capable of reading from or writing to an encrypted data region of the storage apparatus, when the control module is confirmed to be in the ready state and the authentication information matches predetermined authentication information; and (d) controlling the portable electronic apparatus to be incapable of accessing the encrypted data region when the authentication information does not match the predetermined authentication information.

Abstract: The present invention provides a flash memory controller, wherein the flash memory controller includes a read-only memory, a microprocessor and a decoder, wherein the read-only memory is configured to store a program code, the microprocessor is configured to execute the program code to access a flash memory module, and the decoder includes a hard decoding function and a soft decoding function. In the operations of the flash memory controller, when the flash memory controller and the flash memory module are powered-on, the flash memory controller reads data from a specific block of the flash memory module, and the decoder determines if disabling the soft decoding function or not according to a status of the specific block or a status of the data.

Abstract: A method for checking storage units of flash memory of flash memory device includes: writing data into storage units; and performing data read operation to read data from storage units to compare read data with written data to check whether data is correctly written into storage units, and data read operation includes: performing sequential read operation to sequentially select first storage unit and to read data from first storage unit according to serial order numbers; determining whether first storage unit is damaged; accumulating a number of damaged storage units if first storage unit is damaged; determining whether the number of damaged storage units is larger than first threshold number; and exiting sequential read operation and performing random read operation to read data of specific storage unit if the number of damaged storage units is larger than first threshold number.

Abstract: A storage device and a data storing method thereof are provided. The storage device includes a data storage medium and the control unit. The data storage medium includes a data storage area with a plurality of first type of data blocks. When a data reading operation is executed on a current data block of the data storage medium, the control unit determines whether a read count of the current data block is greater than a first threshold, determines whether the current data block is one of the first type of data blocks and generate a determination result according to the result, the control unit selects a plurality of first type of data blocks and switches the selected data blocks to a fast mode. Finally, the control unit moves data stored in the current data block to the selected data blocks under fast mode.

Abstract: A method for recording a duration of use of a data block is disclosed, as well as a data storage device implementing that method. The data block is either an in-use data block or an empty data block. The method includes steps of: receiving and writing data into one of the in-use data blocks and writing a program time and a time interval of the data into the in-use data block. Wherein the time interval is a difference between the program time and an initial program time of the in-use data block, and the initial program time was recorded when the in-use data block wrote a first piece of data.

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Abstract: A data storing method for a data storage device is provided. The data storage device includes a volatile memory and a non-volatile memory. The data storing method includes steps of: designating a data flush block, wherein the data flush block is the non-volatile memory without data buffering function; determining whether a sudden power-off event occurs; and when the sudden power-off event occurs, copying or moving first data stored in the volatile memory to the data flush block. A data storing method after a sudden power-off event occurs is also provided.

Abstract: A data storage device includes a memory controller and a memory device. The memory device includes a current memory block. The memory controller is coupled to the memory device and configured to access the memory device. In response to detection of a sudden power-off that has occurred before the memory device is powered up, the memory controller is configured to find a last valid page and a last valid word line corresponding to the last valid page by scanning a plurality of pages in the current memory block, and determine whether to use one or more empty pages belonging to a word line group that is the same as that of the last valid page according to a read count and an erase count of the current memory block.

Abstract: A data structure for storing specific information of a non-volatile memory is disclosed. To store a file, the non-volatile memory is allocated to provide a first block and a second block to store file content and file system data separately. A root table is maintained on the non-volatile memory, wherein the root table contains usage information of the first block and the second block. When updating the root table to update the usage information of the first block and the second block, the usage information of the first block and the second block is also updated to the second block as metadata. The power restoration procedure is greatly simplified.

Abstract: A data storage device in a two-layer control structure is provided. A control unit of the data storage device has a command processor and a first non-volatile memory (NVM) controller. The command processor is operative to communicate with a host. The first non-volatile memory (NVM) controller operates a first NVM of the data storage device. Earlier than the command processor operates according to a ROM image corresponding to the command processor, the first NVM controller operates according to a ROM image corresponding to the first NVM controller to access the first NVM to get a firmware image for the command processor and loads the command processor with the firmware image.

Abstract: A method for performing access control regarding quality of service (QoS) optimization of a memory device with aid of machine learning an associated apparatus (e.g. the memory device and a controller thereof) are provided. The method may include: performing background scan on the NV memory to collect valley information of voltage distribution of memory cells within the NV memory, and performing machine learning based on a reinforcement learning model according to the valley information, in order to prepare a plurality of tables through the machine learning based on the reinforcement learning model in advance, for use of reading data from the NV memory; during a first time interval, writing first data and read the first data using a first table within the plurality of tables; and during a second time interval, reading the first data using a second table within the plurality of tables.

Abstract: A data storage device includes a memory controller and a memory device. The memory controller includes multiple memory blocks, and each memory block includes multiple pages. The memory controller is coupled to the memory device and configured to access the memory device. In an initialization procedure of the data storage device, the memory controller is configured to determine whether a sudden power-off has occurred during a first write operation to write data to a first memory block, and when a sudden power-off is determined to have occurred during the first write operation, the memory controller is configured to select a second memory block that is and write data to the second memory block in a second write operation.

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Abstract: A method for performing page availability management of a memory device, the associated memory device and electronic device, and page availability management system are provided. The method may include: obtaining a set of page Error Correction Code (ECC) error tables of a non-volatile (NV) memory; based on a predetermined rule, finding respective local risky pages of at least one portion of blocks within a plurality of blocks according to the set of page ECC error tables, respectively, to generate local risky page counts respectively corresponding to page indexes; finding one or more global risky pages corresponding to one or more page indexes of the multiple page indexes according to the local risky page counts; and writing a global risky page table into the memory device, for controlling the memory device to skip using the one or more global risky pages of each of the plurality of blocks.

Abstract: An encoder of a flash memory controller is provided, which includes a barrel shifter module, an inverse matrix calculating circuit and a calculating circuit. The barrel shifter module processes multiple data blocks to generate multiple partial parity blocks including a first portion, a second portion and a third portion. The inverse matrix calculating circuit performs inverse matrix calculating operations on the first portion to generate a first portion of parity blocks. The calculating circuit performs inverse matrix calculating operations on the second portion and the third portion according to the first portion of the parity blocks, to generate a second portion of the parity blocks and a third portion of the parity blocks. The first portion of the parity blocks, the second portion of the parity blocks, and the third portion of the parity blocks serve as multiple parity blocks generated in response to encoding the data blocks.

Abstract: A Universal Flash Storage (UFS) memory module including an input/output interface, a flash memory and a controller, and a method for operating a UFS memory module are disclosed. The flash memory includes: a write buffer portion; and a normal storage portion having a plurality of logic units. The controller includes: a processor; a first register indicating a maximum size of the write buffer portion; a second register indicating an available size of the write buffer portion; and a third. If the third register indicates the UFS memory module is in a shared buffer mode, the write buffer portion only includes a first shared buffer area. If the third register indicates the UFS memory module is in an advanced mode, the write buffer portion includes at least one dedicated buffer area, each corresponding to one of the plurality of logic units.

Abstract: A data storage device including a flash memory and a controller. The controller enables the flash memory to transmit a predetermined parameter stored in the flash memory according to a first predetermined trigger edge of a clock signal and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a first reference parameter in an asynchronous mode. The controller enables the flash memory to switch to a synchronous mode and transmit the predetermined parameter and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a second reference parameter in a detection mode.

Abstract: A storage device and an interface chip thereof are provided, wherein the interface chip can be applied to the storage device. The interface chip comprises a slave interface circuit, a master interface circuit, and a control circuit. The storage device comprises a memory controller and a non-volatile (NV) memory, and the NV memory comprises a plurality of NV memory chips. The slave interface circuit is arranged for coupling the interface chip to the memory controller. The master interface circuit is arranged for coupling the interface chip to a set of NV memory chips within the plurality of NV memory chips. A hierarchical architecture in the storage device comprises the memory controller, the interface chip, and the set of NV memory chips. The control circuit is arranged for controlling operations of the interface chip.

Abstract: A method for managing a memory apparatus including at least one non-volatile (NV) memory element including a plurality of physical blocks includes: obtaining a first host address and first data from a received first access command; obtaining a second host address and second data from a received second access command; linking the first host address to at least a first page of the physical block and linking the second host address to at least a second page of the physical block; storing the first data and second data into the physical block; and selectively erasing a portion of the physical block according to a valid/invalid page count of the physical block, the valid/invalid page count corresponding to accessing pages of the physical block. A difference value of the first host address and the second host address is greater than a number of pages of the physical block.