Abstract: The invention introduces a non-transitory computer program product for reading partial data of a page on multiple planes when executed by a processor core includes program code to: provide a scheduling table; put each flash-memory access command of a command queue into a cell of the scheduling table according to physical address information of the flash-memory access command; select two flash-memory access commands or more for a logical unit number (LUN) according to the content of the scheduling table; drive a flash interface to perform a multi-page read lite (MPR-Lite) operation for reading data requested by the selected flash-memory access commands from the LUN; and reply with the read data to a host.
Abstract: A power recovery technique for a data storage device having a non-volatile memory and a control unit is shown. The non-volatile memory is programmed using one-shot programming, wherein N pages are programmed in one round of one-shot programming and N is a number greater than one. A control unit corrects the final page indicator of an active block of the non-volatile memory in a power recovery procedure to cope with a sudden power-off event, to point the final page indicator to a final page among N pages of one round of one-shot programming.
Abstract: A preheating procedure for a non-volatile memory that can be used in a wide range of ambient temperatures is shown. The controller of the non-volatile memory operates the non-volatile memory to preheat the non-volatile to a temperature target. The controller avoids writing valid data to the non-volatile memory until preheating the non-volatile memory to the temperature target. The controller may write or read dummy data to or from the non-volatile memory until preheating the non-volatile memory to the temperature target.
Abstract: A data storage device with fault-tolerant design. The data storage device has a RAID (Redundant Array of Independent Disks) engine that generates RAID checking code for user data requested in a write command. The user data is programmed to a non-volatile memory according to a target physical address indicated in the write command. The RAID checking code is programmed to the non-volatile memory according to a reserved physical address. The user data and the RAID checking code are programmed to a stripe of pages within a stripe of blocks.
Abstract: A data storage device with a non-volatile memory on which a garbage collection operation is segmented to be accomplished at separate time intervals. Host commands are inserted to be executed between the separate time intervals. A data swap stage or/and an F2H table update stage or/and an H2F table update stage for a garbage collection operation may be segmented to be performed at separate time intervals.
Abstract: The invention introduces a method for internal data movements of a flash memory device, performed by a host, at least including the following steps: generating an internal movement command when detecting that a usage-status for an I/O channel of a solid state disk (SSD) has met a condition; and providing the internal movement command to direct the SSD to perform an internal data-movement operation in the designated I/O channel.
Abstract: A data storage device utilized for storing a plurality of data, wherein the data storage device includes a memory and a controller. The memory includes a plurality of blocks, and each of the blocks includes a plurality of physical pages. The controller is coupled to the memory and maps the logical pages to the physical pages of the memory, and it performs a leaping linear search for the logical pages. The controller searches the Nth logical page of the logical pages according to a predetermined value N. N is a positive integer greater than 1. When the Nth logical page is a currently-used logical page, the controller incrementally decreases the predetermined value N to keep searching the logical pages until a non-currently-used logical page is detected.
Abstract: A method for performing initialization in a memory device, the associated memory device and the controller thereof, and an associated electronic device are provided. The method may include: after a non-volatile (NV) memory within the memory device is powered on, searching for an empty-memory indicator in the NV memory, wherein the empty-memory indicator is applicable to determining whether the NV memory is empty; and according to whether the empty-memory indicator is found or not, selectively skipping or performing a program code search in the NV memory, to complete an initialization process, wherein the initialization process includes at least one initial setting of the memory device, and if the empty-memory indicator is found, the program code search is skipped, otherwise, the program code search is performed.
Abstract: The invention introduces a method for garbage collection, performed by a processing unit, including at least the following steps: executing instructions of a GC (garbage collection) process to direct a first access interface to read data from a storage unit, collect good data from the read data and direct the first access interface to program the good data into a spare block of the storage unit. During the GC process, each time that a timer has counted to a time period, the processing unit directs a second access interface to clock a portion of data requested by a host device out to the host device and resets the timer.
Abstract: A data storage device is provided. The data storage includes: a flash memory, a dynamic random access memory (DRAM), and a memory controller. The flash memory stores a logical-to-physical mapping (L2P) table that is divided into a plurality of group-mapping (G2P) tables, and includes a first logical unit number (LUN) and a second LUN that are respectively controlled by a first chip enable (CE) signal and a second CE signal. The memory controller receives a write command from a host, and forms super page data using logical pages of data in the write command. The memory controller reads one of the group-mapping tables from the first LUN or the second LUN to the DRAM after sequentially enabling the first CE signal and second CE signal to write a first portion and a second portion of the super page data to the first LUN and the second LUN.
Type:
Grant
Filed:
June 3, 2019
Date of Patent:
September 15, 2020
Assignee:
SILICON MOTION, INC.
Inventors:
Chen-Ning Yang, Chien-Chung Chung, Jian-Wei Sun
Abstract: A technology for calibrating device-end operational information of a data storage system is shown. A controller operates a non-volatile memory with reference to operational information. A second type of logical address requested by the host that is different from the first type of logical address used in operating a file system of a host is introduced. As indicated by the second type of logical address, the controller receives calibration information from the host and calibrates the operational information based on the calibration information.
Abstract: A power recovery technique for a data storage device having a non-volatile memory and a control unit is provided. When the data storage device regains power, the control unit writes dummy data to the nonvolatile memory, starting from the next page of a final page indicated by a final page indicator until the first word line group is finished. The first word line group contains an empty page indicated by an empty page indicator. In this manner, user data is protected from being written to an unreliable area.
Abstract: A data storage device includes a flash memory, a controller and a random-access memory. The flash memory includes a plurality of planes, and each plane includes a plurality of blocks. A portion of blocks in each of the planes constitutes a super block, so that the flash memory includes a plurality of super blocks. The controller is coupled to the flash memory. When a first block of at least one first super block of the super blocks is damaged, and a second block of a second super block in the position corresponding to the damaged block is normal, the controller merges the second block of the second super block with the first super block to replace the first block. The random-access memory stores a compression table to record position information about the first block in the first super block and the number information of the second block.
Abstract: A data storage device includes a memory controller and a memory device. The memory controller includes multiple memory blocks each including a first predetermined number of pages. In an SPOR procedure, the memory controller is configured to divide a destination memory block previously utilized in a garbage collection procedure that has not been finished into multiple sub-blocks each including a second predetermined number of pages, sequentially perform a binary search on one or more sub-blocks to determine a first empty page of the destination memory block, sequentially read one or more pages from the first empty page to determine a last valid page of the destination memory block, and re-perform the garbage collection procedure according to the last valid page. The second predetermined number is smaller than the first predetermined number and is a power of 2.
Abstract: A storage apparatus managing method, applied to a first storage apparatus and a second storage apparatus coupled to an electronic apparatus, wherein the first storage apparatus comprises a local registering region and a global registering region, comprising: (a) receiving a read request indicating reading a target data unit from the second storage apparatus; (b) confirming whether the global registering region has the target data unit; (c) if yes, reading the target data unit from the global registering region, if not, confirming whether the local registering region has the target data unit; and (d) reading the target data unit from the local registering region if the local registering region has the target data unit, reading the target data unit from the second storage apparatus if the local registering region does not have the target data unit.
Abstract: A batch automatic test method and a batch automatic test device for solid state disks are provided. The batch automatic test method is used for testing a plurality of solid state disks by a batch automatic test device. The solid state disks are coupled to the batch automatic test device. The batch automatic test method includes the following steps. A plurality of buses of the batch automatic test device are scanned to mark the solid state disks and a system disk. A piece of disk information of each of the solid state disks is shown. Each of the pieces of the disk information includes a disk location of each of the solid state disks. A formatting procedure is synchronously performed on the solid state disks according to the disk locations. After performing the formatting procedure, a burn-in test procedure is automatically and synchronously performed on the solid state disks.
Type:
Grant
Filed:
February 28, 2019
Date of Patent:
September 8, 2020
Assignees:
SHENZHEN SHICHUANGYI ELECTRONICS CO., LTD, SILICON MOTION, INC.
Abstract: A storage device and an interface chip thereof are provided, wherein the interface chip can be applied to the storage device. The interface chip comprises a slave interface circuit, a master interface circuit, and a control circuit. The storage device comprises a memory controller and a non-volatile (NV) memory, and the NV memory comprises a plurality of NV memory chips. The slave interface circuit is arranged for coupling the interface chip to the memory controller. The master interface circuit is arranged for coupling the interface chip to a set of NV memory chips within the plurality of NV memory chips. A hierarchical architecture in the storage device comprises the memory controller, the interface chip, and the set of NV memory chips. The control circuit is arranged for controlling operations of the interface chip.
Abstract: A data storage device includes a data storage medium and a control unit. The control unit is electrically connected to the data storage medium. When switched to a command queue mode, the control unit is configured to receive a queue command comprising at least one task from a host, determine whether the at least one task is a ready-for-execution task, sort at least one ready-for-execution task and selectively reply the host with first queue status information. The first queue status information contains a task quantity corresponding to the at least one ready-for-execution task and at least one task serial number corresponding to the at least one sorted ready-for-execution task.
Abstract: An efficient data storage device is disclosed, which uses a microprocessor and at least one volatile memory to operate a non-volatile memory. The microprocessor allocates the volatile memory to provide a cache area. According to an asynchronous event request (AER) issued by a host, the microprocessor uses the cache area to collect sections of write data requested by the host, programs the sections of write data collected in the cache area to the non-volatile memory together, and reports failed programming of the sections of write data to the host by AER completion information.
Abstract: A method for performing writing management in a memory device, the memory device, and the controller thereof are provided. The method may include: writing first partial data of even-page data into a non-volatile (NV) memory; transmitting a first set of commands without a confirmation command to the NV memory, to write the first partial data and second partial data of the even-page data into an internal buffer within the NV memory; transmitting a second set of commands and the confirmation command to the NV memory, to write the first partial data and the second partial data into a block of the NV memory; writing third partial data of odd-page data into the NV memory; and writing the first and the second partial data into an even page of another block of the NV memory, and writing the third and fourth partial data into an odd page of this block.