Patents Assigned to Silicon Motion, Inc.
  • Patent number: 10754548
    Abstract: A data storage device is provided. The data storage device includes a flash memory and a controller. The flash memory stores a firmware. The firmware includes a plurality of mode page settings, and each mode page setting includes a plurality of mode parameters. The controller receives a mode selection command and a data out message arranged to rewrite a first mode page setting among the plurality of mode page settings from a host. The controller determines whether the data out message will change the mode parameters which cannot be rewritten in the first mode page setting according to the data out message. When the data out message will not change the mode parameters which cannot be rewritten in the first mode page setting, the controller determines whether a plurality of new mode parameters are kept in the flash after the data storage device is turned off.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: August 25, 2020
    Assignee: SILICON MOTION, INC.
    Inventors: Te-Kai Wang, Yu-Da Chen
  • Patent number: 10754566
    Abstract: A data storage device utilized for storing a plurality of data includes a memory and a controller. The memory includes a plurality of blocks, and each of the blocks includes a plurality of physical pages. The controller is coupled to the memory. When the data storage device is initiated, or when the data size read by a host is greater than a threshold value, the controller inspects the status of the data stored by the physical pages of the memory.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: August 25, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Szu-I Yeh
  • Publication number: 20200256913
    Abstract: The invention introduces a method for verifying memory interface, performed by a processing unit, to include: driving a physical layer of a memory interface to pull-high or pull-low a signal voltage on each Input-Output (IO) pin thereof to a preset level according to a setting; obtaining a verification result corresponding to each IO pin from the memory interface; and storing each verification result in a static random access memory (SRAM), thereby enabling a testing host to obtain each verification result of the SRAM through a test interface. The testing host may examine each verification result to know whether any unexpected error has occurred in signals on the IO pins of the memory interface.
    Type: Application
    Filed: August 22, 2019
    Publication date: August 13, 2020
    Applicant: SILICON MOTION, INC.
    Inventor: Wei-Liang Sung
  • Publication number: 20200257462
    Abstract: The invention introduces a method for configuring impedance of memory interfaces, performed by a processing unit, including: setting a first impedance value associated with an on-die termination (ODT) for a receiver of a controller to a first default value; setting a second impedance value associated with a driver variable resistance for a transmitter of a memory device to a second default value; performing tests for test combinations each comprises a third impedance value associated with a driver variable resistance for a transmitter of the controller and a fourth impedance value associated with an ODT for a receiver of the memory device; and storing a test result for each in a predefined location of a static random access memory (SRAM), thereby enabling a calibration host to obtain the test result for each from the SRAM.
    Type: Application
    Filed: July 2, 2019
    Publication date: August 13, 2020
    Applicant: Silicon Motion, Inc.
    Inventors: Wei-Liang SUNG, Chi-Ping CHANG
  • Patent number: 10740013
    Abstract: A block clearing method for a non-volatile data-storage device operates by determining whether a number of data block programmed in a first mode is less than a threshold, selecting a spare block from a spare pool, programming a plurality of data from the selected data blocks into the selected spare block in a second mode, mapping a plurality of logical addresses of the data to a plurality of physical addresses on the selected spare block programmed in the second mode, and releasing the selected data blocks into the spare pool, wherein the selected spare block is able to be programmed in either the first mode or the second mode. Following the determining step, if the determination is true, the method selects a plurality of data blocks programmed in the first mode.
    Type: Grant
    Filed: November 23, 2018
    Date of Patent: August 11, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Yu-Wei Fan
  • Patent number: 10725902
    Abstract: A method for scheduling read commands, performed by a processing unit, includes at least the following steps: receiving a logical read command and a logical address; obtaining a high-level mapping table; obtaining a mapping table block according to the logical address and the high-level mapping table; obtaining a first physical address according to the logical address and the mapping table block; outputting an actual read command and the first physical address to a storage unit to obtain a data; and outputting the data which is responsive to the logical read command. The high-level mapping table includes a plurality of records, and one of the records is utilized to illustrate a second physical address of the mapping table block.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: July 28, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Yang-Chih Shen
  • Patent number: 10719272
    Abstract: Multi-channel accessing of non-volatile memory. A controller uses three kinds of tables to manage cross-channel accessing areas and, accordingly, to access the non-volatile memory through multiple channels. Each cross-channel accessing area includes M storage units, where M is an integer greater than 1. For each cross-channel accessing area, the first table marks whether there is a need for storage unit substitution and points to substitution information. The substitution information is stored in the second table and the third table. For each cross-channel accessing area marked in the first table, the second table stores M bits corresponding to M storage units of the marked cross-channel accessing area for substitution indication, and related substitute storage unit indication is stored in the third table.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: July 21, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Liang-Cheng Chen
  • Patent number: 10719254
    Abstract: A data storage device includes a memory device and a controller. The memory device includes multiple memory blocks. The memory blocks include single-level cell blocks and multiple-level cell blocks. The controller is coupled to the memory device. When the controller executes a predetermined procedure to write data stored in the single-level cell blocks into the multiple-level cell blocks, the controller is configured to determine whether a valid page count corresponding to each single-level cell block is greater than a threshold, and when the valid page count corresponding to more than one single-level cell block is greater than the threshold, the controller is configured to execute a first merge procedure to directly write the data stored in the single-level cell blocks with the valid page count greater than the threshold into one or more of the multiple-level cell blocks.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: July 21, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Wen-Sheng Lin, Yu-Da Chen
  • Patent number: 10714193
    Abstract: A data storage apparatus and a method for preventing data error using the same are provided. The data storage apparatus includes a memory and a memory controller. The memory includes a plurality of blocks. The memory controller is coupled to the memory and configured to perform the following operations: recording a read count of a target block of the memory; performing an error bit check on a free storage space of the target block when the read count of the target block meets a condition; and programming a dummy data to the free storage space of the target block in response to the determination that the check result is negative.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: July 14, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Yu-Hsuan Cheng
  • Patent number: 10713115
    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: July 14, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Publication number: 20200218652
    Abstract: The invention introduces a method for performing data writes into a flash memory, at least including the steps: determining whether at least one host write command that requires to process immediately is presented in a submission queue (SQ) before performing a portion of a Host-Flash mapping (H2F) table update or a GC process; and executing the host write command that requires to process immediately in a batch and then performing the portion of the H2F table update or the GC process when the determination is positive.
    Type: Application
    Filed: June 19, 2019
    Publication date: July 9, 2020
    Applicant: Silicon Motion, Inc.
    Inventor: Kuo-Ting HUANG
  • Publication number: 20200218468
    Abstract: The invention introduces an apparatus for controlling different types of storage units, at least including: an interface and a processing unit. The interface connects at least two types of storage units, which include at least a nonvolatile hybrid memory. The processing unit is configured to operably access data to the different types of storage units through the interface.
    Type: Application
    Filed: December 12, 2019
    Publication date: July 9, 2020
    Applicant: Silicon Motion, Inc.
    Inventor: Sheng-I HSU
  • Patent number: 10705749
    Abstract: A method for performing access control in a memory device, the associated memory device and the controller thereof are provided. The method includes: according to at least one predetermined arrangement pattern, writing a plurality of sets of symbols into a plurality of storage regions of a memory as a plurality of redundant array of independent disks (RAID) groups, respectively; and utilizing a RAID engine circuit in the memory device to perform a plurality of operations related to data protection, such as: determining a series of reading patterns corresponding to the predetermined arrangement pattern; according to a reading pattern of the series of reading patterns, reading a plurality of symbols from each RAID group of the RAID groups; and performing exclusive-OR (XOR) operations on the symbols to convert the symbols into at least one XOR result, for performing data protection.
    Type: Grant
    Filed: September 3, 2018
    Date of Patent: July 7, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Chiao-Wen Cheng
  • Patent number: 10698814
    Abstract: A data storage device includes a memory device and a memory controller. The memory controller is coupled to the memory device and configured to access the memory device and establish a physical to logical address mapping table and a logical address section table. The logical address section table records statuses of a plurality of logical address sections. Each status is utilized to indicate whether the physical to logical address mapping table records any logical address that belongs to the corresponding logical address section. The logical address section table includes a plurality of section bits in a plurality of dimensions. When the memory controller receives a write command to write data of a first predetermined logical address, the memory controller determines the section bit of each dimension corresponding to the first predetermined logical address, and accordingly sets a corresponding digital value for each section bit.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: June 30, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Hsuan-Ping Lin, Chia-Chi Liang
  • Patent number: 10698809
    Abstract: The present invention provides a method for accessing a flash module, wherein the method includes: creating a logical address group table corresponding to a block of the flash module, wherein the logical address group table records states of a plurality of logical address groups, and the state of each logical address group represents if data written into the block has any logical address within the logical address group; when the block is under a garbage collection operation, referring to the logical address group table to read at least one logical address to physical address (L2P) mapping table; and determining valid pages and invalid pages within the block according to the L2P table, for performing the garbage collection operation.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: June 30, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Jie-Hao Lee, Hsuan-Ping Lin
  • Patent number: 10691589
    Abstract: A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.
    Type: Grant
    Filed: December 23, 2018
    Date of Patent: June 23, 2020
    Assignee: Silicon Motion Inc.
    Inventor: Chao-Kuei Hsieh
  • Patent number: 10691569
    Abstract: A system for testing a data storage device includes the data storage device, an electronic device and a computer device. The electronic device includes a host device coupled to the data storage device and communicating with the data storage device via an interface logic. The computer device is coupled to the electronic device and is configured to issue a plurality of commands to test the data storage device in a test procedure. When the electronic device has been successfully started up, the computer device issues a first command to the electronic device to trigger the electronic device to enter a hibernate mode. After waiting for a first predetermined period of time, the computer device issues a second command to the electronic device, so as to wake up the electronic device.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: June 23, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Po-Yi Shih
  • Patent number: 10691358
    Abstract: A method applied into a memory controller coupled between a memory device and a host device wherein the memory device supports at least two different storing modes includes: receiving and buffering data transmitted from the host device; using a first storing mode to store a first data unit into the memory device, a size of the first data unit being not larger than a size of a specific storage unit defined in the memory device; and using a second storing mode, different from the first storing mode, to store a second data unit into the memory device, a size of the second data unit being larger than the size of the specific storage unit.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: June 23, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Ming-Yen Lin
  • Patent number: 10691342
    Abstract: An optimized non-volatile memory operating method. A data storage device has a plurality of non-volatile memory spaces and a plurality of command queues. The command queues are provided to correspond to the non-volatile storage memory one on one. The same channel is shared to operate the non-volatile memory spaces. To deal with the one channel communication technology, the data storage device adopts task switching mechanisms to switch between the different command queues for execution of the operational commands queued in the different command queues.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: June 23, 2020
    Assignee: SILICON MOTION, INC.
    Inventors: Shu-Lei Chen, Ming-Hung Chang
  • Patent number: 10686607
    Abstract: A data storage device including a non-volatile memory and a micro-controller is provided. The non-volatile memory stores a firmware file. The micro-controller is coupled to the non-volatile memory, and performs an encryption procedure on the firmware file. The encryption procedure includes: using a first key and a first algorithm to encrypt the firmware file to generate a signature, using the first key and a second algorithm to scramble the signature to generate a scrambled signature, and attaching the scrambled signature to the firmware file.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: June 16, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Ching-Ke Chen, Yu-Han Hsiao