Abstract: A method for managing a memory apparatus including a non-volatile (NV) memory element having a plurality of physical blocks includes: obtaining a first host address and first data from a first access command; obtaining a second host address and second data from a second access command; linking the first host address to a first page of the physical block and the second host address to a second page of the physical block; storing the first data and second data into the physical block; building a valid page position table and storing the valid page position table in the volatile memory; and building a global page address linking table and storing the global page address linking table in the volatile memory. The valid page position table and the global page address linking table are loaded from the volatile memory and stored to the NV memory element at predetermined time periods.

Abstract: An interface circuit includes multiple signal processing devices and a monitor and calibration module. A process monitor monitors a current or a voltage of a test element to generate a process detection result. A temperature monitor monitors an environment temperature to generate a temperature monitored result. A calibration circuit performs calibration operation on a signal processing device according to a preferred reference value subset to adjust a characteristic value of the signal processing device. A compensation control mechanism operation logic selects the preferred reference value subset from multiple reference value subsets according to the process detection result and the temperature monitored result and generates a calibration control signal to control the calibration operation of the calibration circuit.

Abstract: A technique for accurate communication between a non-volatile memory and its controller. The controller accesses a storage area of the non-volatile memory through data lines, wherein the controller transmits a command through the data lines to access the storage area of the non-volatile memory. The command is further returned from the non-volatile memory to the controller through the data lines for comparison, to determine whether the command is correctly received by the non-volatile memory.

Abstract: A control method of a memory device includes: controlling a flash memory controller to transmit a command to a flash memory module; determining whether the flash memory controller is in an idle state; in response to the flash memory controller being in the idle state, determining whether an idle time of the idle state exceeds a threshold value, wherein the threshold value is less than a time required for the flash memory module to complete executing a write command or an erase command; and in response to the idle time exceeding the threshold value, controlling the flash memory controller to enter a power saving mode to turn off a part of components in the flash memory controller.

Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

Abstract: A memory operation method, comprising: when a first super block of a memory device is a open block (or in programming state), obtaining a first read count of one of a plurality of first memory blocks in the first super block, wherein the first read count is a number of times that data of one of the first memory blocks is read out; determining whether the first read count is larger than a first threshold; and when the first read count is larger than the first threshold, moving a part of the data in the first super block to a safe area in the memory device, wherein the part of the data comprises data in the first memory block.

Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple memory blocks. The memory blocks includes one or more spare memory blocks that are not written with data and one or more predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller is coupled to the memory device and configured to access the memory device. The memory controller is configured to determine a setting value of a number of said one or more predetermined memory blocks according to a number of currently remaining spare memory block(s), a number of the predetermined memory block(s) that has/have been written with data among said one or more predetermined memory blocks and a predetermined threshold, and configure the number of the predetermined memory block(s) as the buffer according to the setting value.

Abstract: An interface circuit includes multiple signal processing devices and a monitor and calibration module including multiple monitoring circuits, multiple calibration circuits and a compensation control mechanism operation logic. The monitoring circuits monitor a reception signal, a transmission signal, a power supplying voltage and a ground voltage to correspondingly generate monitored results. The calibration circuits perform a calibration operation on at least one signal processing device to adjust a characteristic value of the signal processing device.

Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple memory blocks which include one or more spare memory blocks not written with data and one or more predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller obtains a total number of remaining erasable count of the memory blocks and determines a setting value of a number of said one or more predetermined memory blocks according to a number of currently remaining spare memory block(s), a number of the predetermined memory block(s) that has/have been written with data among said one or more predetermined memory blocks, a predetermined threshold and the total number of remaining erasable count of the memory blocks, and configures the number of the predetermined memory block(s) as the buffer according to the setting value.

Abstract: A method for performing memory access of a Flash cell of a Flash memory includes: performing a series of sensing operations respectively corresponding to a plurality of sensing voltages, wherein a sensing voltage of a specific sensing operation of the series of sensing operations has a sensing voltage determined according to a result of an initial sensing operation of the series of sensing operations; determining a threshold voltage of the Flash cell according to at least a digital value generated by the series of sensing operations; and using the determined threshold voltage to perform soft decoding of the Flash cell.

Abstract: A bridge device includes a first controller and a second controller. The first controller includes a first transmission interface. The second controller includes a second transmission interface. The first transmission interface and the second transmission interface are flash memory interfaces. In a program mode, the first transmission interface receives a first command from the second transmission interface and obtains first transfer data from a bus in response to the first command. A value of the first command is optionally set to a first value or a second value. The first value indicates a memory command transfer operation in a first direction and the second value indicates a memory data transfer operation in the first direction. The first transmission interface processes the first transfer data according to the value of the first command to obtain a memory command or written data.

Abstract: A method for performing data access management of a memory device in predetermined communications architecture with aid of unbalanced table update size and associated apparatus are provided. The memory device may be arranged to receive a set of first commands, receive a set of first data with a first active block according to the set of first commands, and update a temporary physical-to-logical (P2L) address mapping table corresponding to the first active block, and determine a selected table update size among multiple predetermined table update sizes such as multiple table entry counts and update at least one logical-to-physical address mapping table according to a set of P2L table entries corresponding to the selected table update size in the temporary P2L address mapping table, where the table update size may be dynamically changed for enhancing overall performance.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for executing host write commands.

Abstract: The invention relates to a method and an apparatus for executing Structural Query Language (SQL) instructions in a Solid-state Storage Device (SSD). The apparatus includes: a processing unit; and a database accelerator. The processing unit is arranged operably to obtain an SQL query from a host side. The database accelerator is arranged operably to parse the SQL query according an SQL syntax tree to generate a series of table tasks to execute; and during the execution of the table tasks, read tables from a flash module through the processing unit, generate intermediate tables and sub-tables based on the read tables, and perform an arithmetic computation, a logical computation or both on a specific field in one intermediate table to generate a final dataset. The processing unit is arranged operably to reply to the host side with the final dataset.

Abstract: The invention introduces an apparatus and a method for expanding round keys during data encryption. The method includes: configuring a word-processing circuitry to operate in a first mode to calculate a first intermediate calculation result corresponding to an even-number round key according to a last double word of a 0th double word to a 7th double word in each even-number clock cycle starting from a 2nd clock cycle; and configuring the word-processing circuitry to operate in a second mode to calculate a second intermediate calculation result corresponding to an odd-number round key according to the last double word of the 0th double word to the 7th double word in each odd-number clock cycle starting from a 3rd clock cycle. In the first mode, a first data path is formed in the word-processing circuitry, which includes a word split circuitry, a rotate-word circuitry, a substitute-word circuitry, a round-constant circuitry and a word concatenation circuitry.

Abstract: A method for performing data access control of a memory device includes: receiving a plurality of host commands from a host device for performing data access upon a non-volatile (NV) memory according to the plurality of host commands, wherein the data access includes data reading; and performing a read optimization procedure for maintaining correctness of the data reading, for example: performing reading operation to obtain multiple channel values; performing compression operation to convert multiple first soft bits in any channel value into multiple second soft bits, to generate a compressed channel value for being buffered in volatile memory; reading multiple compressed channel values from the volatile memory; and utilizing a low-density parity-check (LDPC) code decoding engine circuit to perform LDPC code decoding according to the multiple compressed channel values, and utilizing an error recovery circuit to perform error recovery operation according to the multiple channel values, to generate error-free d

Abstract: A video wall system with software running on a host computer and a video wall control device is shown. Using the software, the user inputs the size of each screen of a video wall and, accordingly, the delay time for each row of screens of the video wall is calculated. The video wall control device couples the host computer to the screens. The video wall control device outputs a plurality of split videos to the different screens through separated output ports, and drives each row of screens to display according to the delay time calculated for the row of screens.

Abstract: A flash memory controller is used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface and includes an input/output (I/O) circuit and a processor. The I/O circuit is coupled to the flash memory device through the specific communication interface, and used for sending commands and data between the flash memory device and the processor. The processor is used for controlling the I/O circuit sending a specific boundary check command signal or a specific boundary check set-feature signal via the specific communication interface to the flash memory device, to make the flash memory device read out more page data of multiple page units from a specific block in the memory cell array and to make the flash memory device determine whether the multiple page units are empty pages.

Abstract: A method for performing access management of a memory device in a predetermined communications architecture with aid of automatic parameter setting and associated apparatus are provided. The method includes: utilizing the memory controller to set at least one write booster static parameter of a write booster function of the memory device; utilizing the memory controller to perform device initialization corresponding to at least one initialization phase of the memory device; and after completing the device initialization corresponding to the at least one initialization phase, performing at least one adaptive flag-setting operation, for setting at least one write booster flag among a plurality of write booster flags of the write booster function, wherein the at least one write booster flag includes a first write booster flag acting as a write booster switch. The adaptive flag-setting operation includes setting the first write booster flag to enable the write booster function by default.

Abstract: A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.