Abstract: Disclosed is a memory controller, a method for controlling a memory controller and a memory device. The memory controller comprises a first interface circuit configured to communicate with a host, a second interface circuit comprising at least one pin, and a control circuit coupled to the first and second interface circuits. Wherein the control circuit is configured to perform an initialization operation via the first interface circuit, and control the at least one pin of the second interface circuit to output a signal indicating a status of the initialization operation. Wherein the signal comprises a dynamic pattern during a processing phase of the initialization operation and a static pattern corresponding to an operation result during a completion phase of the initialization operation.

Abstract: A data storage device that performs instruction scheduling at the device side. The data storage device has a non-volatile memory, and a controller configured to operate the non-volatile memory in response to requests from the host side. The controller has an instruction cache operative to cache instructions issued from the host side. Based on information carried by the instructions, the controller schedules and executes the instructions to operate the non-volatile memory.

Abstract: The disclosure introduces a method for handling a garbage collection (GC) process, performed by a processing unit of a flash controller, to include: detecting that a portable storage device is inserted into a host equipment; operating the portable storage device in a working state; determining whether a transmission bandwidth of a flash I/F is higher than a maximum transmission bandwidth of a host interface (I/F); if so, inserting operations of the GC process during an execution of a host command in the working state; resetting a working expiration timer for counting a specified period of time each time after receiving any host command; and in response to detecting that the working expiration timer reaches the specified period of time, causing the portable storage device to leave the working state and enter a power saving state.

Abstract: A decoding method includes: receiving and storing input data as a channel value in a channel value memory in a form of codeword; generating a posterior probability and a variable-to-check message according to a specific chunk of the channel value; converting the variable-to-check message from variable node domain into check node domain to generate a converted variable-to-check message; using a check node unit to generate a check-to-variable message according to the converted variable-to-check message; converting the check-to-variable message from check node domain into variable node domain to generate a converted check-to-variable message; determining whether to flip at least one bit of the specific chunk according to the posterior probability; and, determining whether to ignore and skip execution of decoding calculation for the specific chunk in a next iterative decoding operation according to whether a decoding calculation result in a current iterative decoding operation matches with a specific condition.

Abstract: The present invention provides a decoding method, which includes steps of: receiving data from a flash memory module; generating syndromes corresponding to the data according to the data and a parity check matrix; storing decoding information corresponding to only a portion of the data into a memory; iteratively updating the syndromes and the decoding information stored in the memory until the updated syndromes meet a specific condition; and generating decoded data according to the updated syndromes and the updated decoded information.

Abstract: Provided are a data storage device and a decoding combination selecting method. The data storage device includes a non-volatile memory and a processing circuit. The non-volatile memory includes a plurality of blocks. Each block includes a plurality of pages. A decoding combination selecting method is executed by the processing circuit to include: periodically reading a page in the non-volatile memory to update state parameters of a first block including the page in a block state table; and selecting one of a plurality of decoding combinations based on the state parameters of the first block in the block state table to decode the first block. The state parameters include a charge leakage degree value, a potential offset degree value, a first offset voltage and a second offset voltage, and a first bit number and a second bit number respectively corresponding to the first offset voltage and the second offset voltage.

Abstract: A method for performing data protection control of a memory device with aid of selective soft-bit transmission and associated apparatus are provided, where the memory device may include a memory controller and a non-volatile (NV) memory. The method may include: sending at least one read command as well as a controller-side indication, the controller-side indication for selectively enabling the selective soft-bit transmission at the NV memory, to the NV memory for obtaining soft-decoding information regarding a first page within a first block among the plurality of blocks, wherein the first page is arranged to store first data; and receiving the soft-decoding information as well as a memory-side indication from the NV memory, wherein the memory-side indication at a first cycle is arranged to indicate whether the NV memory is going to transmit at least one soft bit at a second cycle, the second cycle coming after the first cycle.

Abstract: A decoding method includes: using a syndrome calculation check circuit to calculate a syndrome value of variable node Vi of a parity check matrix based on multiple input bits; rotating the syndrome value of variable node Vi into the direction of variable node Vi+1 to generate an estimated syndrome value of variable node Vi+1; rotating the syndrome value of variable node Vi?1 into the direction of variable node Vi+? to generate a rotated syndrome information; performing a weighted-sum calculation based on multiple rotated syndrome information to generate a flipping function value; and comparing the flipping function value with a flipping threshold to generate a flipping result; the syndrome calculation check circuit determines whether to modify/flip a specific bit according to the flipping result.

Abstract: A decoding method includes: generating a variable-to-check message and a log-likely ratio according a specific codeword; converting the variable-to-check message from variable node domain into check node domain to generate a converted variable-to-check message; generating a check-to-variable message according to the converted variable-to-check message; converting the check-to-variable message from check node domain into variable node domain to generate a converted check-to-variable message; updating the variable-to-check message and the log-likely ratio based on the converted check-to-variable message; performing a hard decision according to the log-likely ratio to determine whether flip bit(s); and, for specific data to be stored into a first memory macro, enabling a write operation of a portion of first physical sub-memories and disabling a write operation of another portion of first physical sub-memories.

Abstract: The invention introduces a method for performing a sudden power off recovery (SPOR) process, performed by a processing unit of a flash controller, to include: performing operations for the SPOR process after regaining power; and performing operations for a reduced garbage collection (GC) process. An execution time of the operations for the SPOR process and the reduced GC process is limited to a preset time that a host side waits for a completion of the SPOR process by the flash controller.

Abstract: The invention introduces a method for handling a garbage collection (GC) process, performed by a processing unit of a flash controller, to include: detecting that a portable storage device is inserted into a host equipment; obtaining a maximum transmission bandwidth of a host interface (I/F); determining that a transmission bandwidth of a flash I/F is higher than the maximum transmission bandwidth of the host I/F; and in response to a determination that the transmission bandwidth of the flash I/F is higher than the maximum transmission bandwidth of the host I/F, inserting operations of the GC process during an execution of a host command.

Abstract: A method for performing read reference voltage management on a flash memory includes: managing a first self-learning table based on one or more read retry operations performed using hard-decision decoding; managing a second self-learning table based on one or more read retry operations performed using soft-decision decoding; managing a sticky table based on a read reference voltage level or a read reference voltage level set used in a most recent successful read retry operation, wherein the read reference voltage level or the read reference voltage level set is derived from at least one of the first self-learning table, the second self-learning table, and a read retry operation using soft-decision decoding; and performing a normal read operation based on the sticky table.

Abstract: A method for controlling a plurality of logical units of a flash memory includes: transmitting on-die termination (ODT) enabling control information over a control bus corresponding to the plurality of logical units through a data transmission start command to enable ODT operation of one or more non-target logical units; and transmitting ODT disabling control information over the control bus through a data transmission terminate command or a data transmission pause command to disable ODT operation of the one or more non-target logical units.

Abstract: A memory controller for controlling a flash memory includes a parallel accessing control circuit. The parallel accessing control circuit is coupled to a command and address (CA) bus, a first data bus, and a second data bus that are respectively coupled to a plurality of first memory units and a plurality of second memory units of the flash memory. The parallel accessing control circuit includes a CA sequencer configured to manage control signals and memory addresses that are transmitted over the CA bus; a first data input/output (DQ) sequencer configured to, through the first data bus, transmit/receive a first portion of encoded write/read data to/from one of first memory units; and a second DQ sequencer, configured to, through the second data bus, transmit/receive a second portion of the encoded write/read data to/from one of second memory units.

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Abstract: A reliability control technology for non-volatile memory is shown. A non-volatile memory has a plurality of blocks. For each block, the processor records a time stamp about programming of at least one page in the block. The processor performs a reliability check on the target block that corresponds to a time stamp exceeding a critical time limit and, if the reliability check shows that the target block does not meet a reliability standard, the processor moves data from the target block to a spare space for safe migration.

Abstract: A memory controller for controlling a flash memory includes a parallel accessing control circuit. The parallel accessing control circuit is coupled to a command and address (CA) bus, a first data bus, and a second data bus that are respectively coupled to a plurality of first memory units and a plurality of second memory units of the flash memory. The parallel accessing control circuit includes a CA sequencer configured to manage control signals and memory addresses that are transmitted over the CA bus; a first data input/output (DQ) sequencer configured to, through the first data bus, transmit/receive a first portion of encoded write/read data to/from one of first memory units; and a second DQ sequencer, configured to, through the second data bus, transmit/receive a second portion of the encoded write/read data to/from one of second memory units.

Abstract: A flash memory controller includes a controller circuit and a scheduler circuit. The controller circuit receives a multi-plane read command signal sent from a host device to respectively read data of storage pages, corresponding to the carried address information, on multiple memory planes within a flash memory. The controller circuit stores the first read commands in the first pending list and stores the second read commands in the second pending list. The scheduler circuit reorders the read commands stored in the first and second pending lists to make first data output time intervals be staggered and not overlap with second data output time intervals.

Abstract: A memory controller is provided, which includes a processor having a plurality of processing cores, and a lookup acceleration circuit. The lookup acceleration circuit includes a message processing circuit and a logical-to-physical mapping table lookup circuit. The message processing circuit receives request messages from the processing cores using request queues, and puts an incoming request message to a collision pending queue in response to detection of a collision between a first logical address range within the incoming request message and second logical address ranges within message contexts corresponding to active request messages. The logical-to-physical mapping table lookup circuit looks up a logical-physical mapping table in a volatile memory to convert the second logical address ranges into first physical addresses. The message processing circuit performs memory access operations corresponding to the active request messages on the volatile memory using the first physical addresses.