Abstract: A decoding method includes: generating a variable-to-check message and a log-likely ratio according a specific codeword; converting the variable-to-check message from variable node domain into check node domain to generate a converted variable-to-check message; generating a check-to-variable message according to the converted variable-to-check message; converting the check-to-variable message from check node domain into variable node domain to generate a converted check-to-variable message; updating the variable-to-check message and the log-likely ratio based on the converted check-to-variable message; performing a hard decision according to the log-likely ratio to determine whether flip bit(s); and, for specific data to be stored into a first memory macro, enabling a write operation of a portion of first physical sub-memories and disabling a write operation of another portion of first physical sub-memories.

Abstract: The invention introduces a method for performing a sudden power off recovery (SPOR) process, performed by a processing unit of a flash controller, to include: performing operations for the SPOR process after regaining power; and performing operations for a reduced garbage collection (GC) process. An execution time of the operations for the SPOR process and the reduced GC process is limited to a preset time that a host side waits for a completion of the SPOR process by the flash controller.

Abstract: The present invention provides a method for controlling a flash memory module. The method includes the steps of: after the flash memory module is powered on, determining whether the flash memory module encountered an abnormal power failure before the flash memory module is powered on; if the flash memory module encounters the abnormal power failure before the flash memory module is powered on, determining a last super block written by the flash memory module before powering on, where the super block includes multiple first blocks; determining a last rewritten page of the super block; determining a check range of the super block according to the last written page of the super block; determining a data weak region of the super block by reading the pages of the check range; and moving data in the weak data region to other regions of the super block or to another super block.

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Abstract: A flash memory controller includes a controller circuit and a scheduler circuit. The controller circuit receives a multi-plane read command signal sent from a host device to respectively read data of storage pages, corresponding to the carried address information, on multiple memory planes within a flash memory. The controller circuit stores the first read commands in the first pending list and stores the second read commands in the second pending list. The scheduler circuit reorders the read commands stored in the first and second pending lists to make first data output time intervals be staggered and not overlap with second data output time intervals.

Abstract: An error handling method for use in a flash memory includes: in response to read data on which a decoding failure occurs or written data on which a programming failure occurs, determining verification data corresponding to the read data or the written data; according to the verification data, selecting data to be moved from the flash memory; and performing a data movement operation to move the data to be moved to a target storage space in the flash memory.

Abstract: A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.

Abstract: A flash memory controller includes a controller circuit and a scheduler circuit. The controller circuit receives a multi-plane read command signal sent from a host device to respectively read data of storage pages, corresponding to the carried address information, on multiple memory planes within a flash memory. The controller circuit stores the first read commands in the first pending list and stores the second read commands in the second pending list. The scheduler circuit reorders the read commands stored in the first and second pending lists to make first data output time intervals be staggered and not overlap with second data output time intervals.

Abstract: A block cipher method of a flash memory controller includes: encrypting a seed value to generate an encrypted seed value in a first/second block cipher mode according to a second key; multiplying the encrypted seed value with ?j according to a mode selection signal to generate a j-th multiplication result; performing a first XOR operation upon the j-th multiplication result and a j-th plaintext block to generate a first XOR result; encrypting the first XOR result to generate an encrypted XOR result in the first/second block cipher mode according to a first key; and, performing a second XOR operation upon the j-th multiplication result and the encrypted XOR result to generate a second XOR result as a j-th ciphertext block; the multiplying step operating in the first/second block cipher mode is determined by either the mode selection signal generated from a microcontroller or recorded in a 0-th plaintext block.

Abstract: The present invention provides a control method of a flash memory controller. The flash memory controller is coupled between a host device and a flash memory module, and the flash memory controller is configured to receive a command from the host device to access the flash memory module; and the control method comprises: setting a first bandwidth for communicating with the host device; determining a reference data rate according to configuration information of the flash memory module; determining if the first bandwidth far exceeds a required bandwidth according to the reference data rate; and if it is determined that the first bandwidth far exceeds the required bandwidth, setting a second bandwidth lower than the first bandwidth, for communicating with the host device.

Abstract: A decoding method includes: providing channel value memory to store input data as a channel value; providing sign memory to store a sign value; providing gradient descent bit memory to store differential information of a channel value; providing variable node unit to generate a first output value and a second output value according to the channel value; converting first output value into a converted first output value from variable node domain into check node domain; providing check node unit to generate check-to-variable message according to the converted first output value or the sign value stored in the sign memory; converting the check-to-variable message into a converted check-to-variable message from check node domain into variable node domain and transmitting the converted check-to-variable message into the variable node domain; and, deciding output data according to channel value and differential information stored in gradient descent bit memory.

Abstract: A method for performing access control of a memory device with aid of expander architecture and associated apparatus are provided, where the memory device may include a memory controller and a non-volatile (NV) memory. The method may include: sending at least one command from the memory controller to the NV memory through an input-output-expander (IO-expander) circuit, with the IO-expander circuit being coupled between the memory controller and the NV memory, in order to start performing at least one access operation on the plurality of NV memory elements via multiple channels, respectively; and during performing any access operation among the at least one access operation, utilizing the IO-expander circuit to expand IO control of the memory controller over the NV memory, for accessing at least one NV memory element corresponding to any sub-channel among a plurality of sub-channels, the plurality of sub-channels split from a single channel among the multiple channels.

Abstract: A method for performing data protection control of a memory device with aid of selective soft-bit transmission and associated apparatus are provided, where the memory device may include a memory controller and a non-volatile (NV) memory. The method may include: sending at least one read command as well as a controller-side indication, the controller-side indication for selectively enabling the selective soft-bit transmission at the NV memory, to the NV memory for obtaining soft-decoding information regarding a first page within a first block among the plurality of blocks, wherein the first page is arranged to store first data; and receiving the soft-decoding information as well as a memory-side indication from the NV memory, wherein the memory-side indication at a first cycle is arranged to indicate whether the NV memory is going to transmit at least one soft bit at a second cycle, the second cycle coming after the first cycle.

Abstract: A coding method of a flash memory controller includes: performing a local encoding operation upon a data unit to be written into a portion of a page unit of the flash memory device and to perform a global encoding operation upon multiple data units to be written into the page unit according to a coding matrix so as to generate and write error correction code data into the page unit; performing a local decoding operation upon the data unit read from the portion of the page unit and to perform a global decoding operation upon the multiple data units read from the page unit according to the error correction code data corresponding to the coding matrix to obtain correct data of the page unit; and, dynamically determining the coding matrix to dynamically select a coding mode.

Abstract: A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface. The flash memory controller sends an error injection set-feature signal to the flash memory device through the specific communication interface to configure an operation of a debug circuit of the flash memory device to make the debug circuit automatically generate debug information of an access operation of an access command signal sent from the flash memory controller, transmit the generated debug information from the flash memory device to the flash memory controller via the I/O control circuit and the specific communication interface, with actually controlling a memory cell array of flash memory device generating failure errors.

Abstract: A clock phase control circuit includes a sampling circuit and a phase monitoring circuit. The sampling circuit receives a plurality of reference clock signals and, in response to a read command, samples data read from a memory device according to the reference clock signals to obtain a plurality of sampling results. The reference clock signals are generated based on a fundamental clock signal with different candidate phases. The phase monitoring circuit receives the sampling results and determines an optimal phase according to the sampling results. The data read from the memory device comprises data in one or more data blocks which are sequentially received in response to the read command. In response to an end of each data block, a sampling phase of the fundamental clock signal to sample the data read from the memory device is adjusted according to the optimal phase.

Abstract: A buffer management control device for use in a flash memory controller includes: a flag table and a flag management engine. The flag table is configured track availability status of a plurality of allocation units within a shared memory of the flash memory controller. The flag management engine is configured to assign one or more allocation units from the plurality of allocation units for buffering read data related to a host read command, and update the flag table according to the one or more assigned allocation units, thereby indicating that the one or more assigned allocation units are occupied.

Abstract: A control method of a memory device includes: reading and decoding first data of a first chunk, wherein the first chunk is located in a first data page of a super data page, and the super data page includes multiple data pages respectively located in multiple data planes; in response to the first chunk failing to be decoded, obtaining data of multiple corresponding chunks of the first chunk, wherein the multiple corresponding chunks are located in other data pages of the super data page; and in response to all of the data in the multiple corresponding chunks not being successfully decoded, determining whether to give up the decoding operation of the first chunk according to a symptom weight of the first chunk and at least one symptom weight of at least one corresponding chunk.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller maintains a write count for each sub-region of the memory device. When the memory controller has selected one or more sub-regions to perform a data rearrangement procedure, the memory controller further determines whether a selected sub-region is a hot-write sub-region according to the write count corresponding to the selected sub-region. When the memory controller determines that the selected sub-region is not a hot-write sub-region, the memory controller performs the data rearrangement procedure on the selected sub-region to move data corresponding to logical addresses belonging to the selected sub-region to a memory space of the memory device having continuous physical addresses. When the memory controller determines that the selected sub-region is a hot-write sub-region, the memory controller does not perform the data rearrangement procedure on the selected sub-region.

Abstract: Garbage collection technology for non-volatile memory is shown. The processor starts valid data determination from a starting source block, selects a first logical-to-physical address mapping sub-table corresponding to a first valid data in the starting source block as a scan target, and scans the scan target to identify and collect valid data to be programmed to a destination block. After a full scan of the scan target, the processor checks the starting source block to obtain second valid data that has not yet been collected and programmed to the destination block. The processor selects a second logical-to-physical address mapping sub-table that corresponds to the second valid data as the new scan target. The processor scans the new scan target to collect and program valid data to the destination block. Every time a logical-to-physical address mapping sub-table is downloaded into the controller's memory, it is fully scanned.