Patents Assigned to Siltronic AG
  • Cleaning method of semiconductor wafer
    Patent number: 10121649
    Abstract: A wax removal method uniformly removes wax adhering to a wafer surface and reduces the problems of re-adhesion of particles and filter clogging of a cleaning bath during cleaning. The method uses cleaning liquid which contains microbubbles.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: November 6, 2018
    Assignee: SILTRONIC AG
    Inventor: Teruo Haibara
  • Method of supporting a growing single crystal during crystallization of the single crystal according to the FZ method
    Patent number: 10094042
    Abstract: A growing single crystal is supported in the region of a conical section of the single crystal via a supporting body during crystallization of the single crystal by the FZ method. The method comprises pressing the supporting body against the conical section of the growing single crystal at a temperature at which a first material of the supporting body becomes soft, and continuing pressing the supporting body against the conical section of the growing single crystal until the first material and a second material of the supporting body that remains hard at the cited temperature touch the conical section of the growing single crystal.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: October 9, 2018
    Assignee: SILTRONIC AG
    Inventors: Kurt Niederer, Helmut Teroerde, Josef Berger, Goetz Meisterernst, Frank Muemmler, Simon Zitzelsberger
  • METHOD FOR PRODUCING A SEMICONDUCTOR WAFER WITH EPITAXIAL LAYER IN A DEPOSITION CHAMBER, APPARATUS FOR PRODUCING A SEMICONDUCTOR WAFER WITH EPITAXIAL LAYER, AND SEMICONDUCTOR WAFER WITH EPITAXIAL LAYER
    Publication number: 20180282900
    Abstract: Semiconductor wafers with an epitaxial layer are produced in a deposition chamber by placing a substrate wafer in the edge region of the rear side of the substrate wafer onto a placement area of a susceptor; loading the deposition chamber with the susceptor and the substrate wafer lying on the susceptor by contacting the susceptor and transporting the susceptor and the substrate wafer lying on the susceptor from a load lock chamber into the deposition chamber; depositing an epitaxial layer on the substrate wafer; and unloading the deposition chamber by contacting the susceptor and transporting the susceptor and a semiconductor wafer with epitaxial layer, the semiconductor wafer having been produced in the course of depositing the epitaxial layer and lying on the susceptor, from the deposition chamber into the load lock chamber.
    Type: Application
    Filed: November 24, 2016
    Publication date: October 4, 2018
    Applicant: SILTRONIC AG
    Inventors: Patrick MOOS, Reinhard SCHAUER
  • Susceptor For Holding A Semiconductor Wafer Having An Orientation Notch, A Method For Depositing A Layer On A Semiconductor Wafer, And Semiconductor Wafer
    Publication number: 20180211923
    Abstract: A semiconductor wafer processing susceptor for holding a wafer having an orientation notch during deposition of a layer on the wafer, having a placement surface for supporting the semiconductor wafer in the rear edge region of the wafer, the placement surface having a stepped outer delimitation, and an indentation of the outer delimitation of the placement surface for placement of the partial region of the edge region of the rear side of the wafer in which the orientation notch is located onto a partial region of the placement surface delimited by the indentation of the outer delimitation of the placement surface. The susceptor is used in a method for depositing a layer on a wafer having an orientation notch, and wafers made of monocrystalline silicon upon which layers are deposited using the susceptor have greater local flatness on both front and rear sides proximate the orientation notch.
    Type: Application
    Filed: March 22, 2018
    Publication date: July 26, 2018
    Applicant: SILTRONIC AG
    Inventors: Reinhard SCHAUER, Christian HAGER
  • METHOD FOR THE THERMAL TREATMENT OF GRANULAR MATERIAL COMPOSED OF SILICON, GRANULAR MATERIAL COMPOSED OF SILICON, AND METHOD FOR PRODUCING A MONOCRYSTAL COMPOSED OF SILICON
    Publication number: 20180194633
    Abstract: Granular silicon which is especially useful in reducing dislocations and gas inclusions of single crystals prepared therefrom is produced by a heat treatment in which a process gas flowing through a plasma chamber heats granular silicon, and the heated granular silicon is transported counter-currently through the plasma chamber, melting an outer periphery of the granular silicon, which then recrystallizes, producing an exterior with a lower concentration of crystal grains than the interior of the granules.
    Type: Application
    Filed: July 1, 2016
    Publication date: July 12, 2018
    Applicant: SILTRONIC AG
    Inventor: Georg BRENNINGER
  • SCREEN PLATE FOR SCREENING PLANTS FOR MECHANICAL CLASSIFICATION OF POLYSILICON
    Publication number: 20180185882
    Abstract: Polysilicon chunks or granules are classified into size fractions using a mechanical screen having a profiled surface having peaks and valleys, and terminating in widening slots through which a polysilicon size fraction falls. The device is effective and the slots are resistant to clogging.
    Type: Application
    Filed: March 15, 2016
    Publication date: July 5, 2018
    Applicants: SILTRONIC AG, WACKER CHEMIE AG
    Inventors: Andreas BERGMANN, Thomas BUSCHHARDT, Simon EHRENSCHWENDTNER, Christian FRAUNHOFER
  • Method for pulling a single crystal composed of silicon from a melt contained in a crucible, and single crystal produced thereby
    Patent number: 9988739
    Abstract: Silicon single crystals are pulled from a melt in a crucible, the single crystal surrounded by a heat shield, the lower end of which is a distance h from the melt surface, wherein gas flows downward between the single crystal and the heat shield, outward between the lower end of the heat shield and the melt, and then upward in the region outside the heat shield. The internal diameter of the heat shield at its lower end is 55 mm or more than the diameter of the single crystal, and the radial width of the heat shield at its lower end is not more than 20% of the diameter of the single crystal. Highly doped single crystals pulled accordingly have a void concentration ?50 m?3.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: June 5, 2018
    Assignee: SILTRONIC AG
    Inventors: Erich Gmeilbauer, Robert Vorbuchner, Martin Weber
  • Susceptor for holding a semiconductor wafer having an orientation notch, a method for depositing a layer on a semiconductor wafer, and semiconductor wafer
    Patent number: 9991208
    Abstract: A semiconductor wafer processing susceptor for holding a wafer having an orientation notch during deposition of a layer on the wafer, having a placement surface for supporting the semiconductor wafer in the rear edge region of the wafer, the placement surface having a stepped outer delimitation, and an indentation of the outer delimitation of the placement surface for placement of the partial region of the edge region of the rear side of the wafer in which the orientation notch is located onto a partial region of the placement surface delimited by the indentation of the outer delimitation of the placement surface. The susceptor is used in a method for depositing a layer on a wafer having an orientation notch, and wafers made of monocrystalline silicon upon which layers are deposited using the susceptor have greater local flatness on both front and rear sides proximate the orientation notch.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: June 5, 2018
    Assignee: SILTRONIC AG
    Inventors: Reinhard Schauer, Christian Hager
  • Method for growing a single crystal by crystallizing the single crystal from a float zone
    Patent number: 9932691
    Abstract: A single crystal is grown in a float zone which is inductively heated and the crystallizing single crystal is rotated in a direction of rotation which is periodically reversed at intervals in accordance with an alternating plan, wherein a dwell time during which the single crystal is in a state of rest because of the reversal of the direction of rotation is limited to no more than 60 ms.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: April 3, 2018
    Assignee: SILTRONIC AG
    Inventors: Georg Raming, Ludwig Altmannshofer, Gundars Ratnieks, Martin Moeller, Frank Muemmler
  • Device for producing a monocrystal by crystallizing said monocrystal in a melting area
    Patent number: 9932690
    Abstract: A device for producing a single crystal by crystallizing the single crystal in a melt zone, comprising a housing, an inductor for generating heat in the melt zone, a reheater which surrounds and applies thermal radiation to the crystallizing single crystal, and a separating bottom which delimits downward an intermediate space between the reheater and a wall of the housing at a lower end of the reheater.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: April 3, 2018
    Assignee: SILTRONIC AG
    Inventors: Georg Raming, Ludwig Altmannshofer
  • Semiconductor wafer and a method for producing the semiconductor wafer
    Patent number: 9923050
    Abstract: A semiconductor wafer has a silicon single crystal substrate having a top surface and a stack of layers covering the top surface, the stack of layers containing an AlN nucleation layer covering the top surface of the silicon single crystal substrate, wherein the top surface of the silicon single crystal substrate has a crystal lattice orientation which is off-oriented with respect to the {111}-plane, the normal to the top surface being inclined with respect to the <111>-direction toward the <11-2>-direction by an angle ? of not less than 0.3° and not more than 6°, the azimuthal tolerance of the inclination being ±0.1°; and an AlGaN buffer layer which covers the AlN nucleation layer and contains one or more AlxGa1-xN layers, wherein 0<×<1.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: March 20, 2018
    Assignees: SILTRONIC AG, IMEC VZW
    Inventors: Sarad Bahadur Thapa, Ming Zhao, Peter Storck, Norbert Werner
  • EPITAXIALLY COATED SEMICONDUCTOR WAFER, AND METHOD FOR PRODUCING AN EPITAXIALLY COATED SEMICONDUCTOR WAFER
    Publication number: 20180047586
    Abstract: Epitaxial wafers with a high concentration of BMD nuclei or developed BMDs just below a denuded zone, and having low surface roughness, are produced by forming an oxynitride layer on a purposefully oxidized epitaxial layer by a short RTA treatment in a nitriding atmosphere, removing the oxynitride layer, and then polishing the epitaxial surface.
    Type: Application
    Filed: October 29, 2015
    Publication date: February 15, 2018
    Applicant: Siltronic AG
    Inventors: Timo MUELLER, Michael GEHMLICH, Frank FALLER
  • SEMICONDUCTOR WAFER COMPRISING A MONOCRYSTALLINE GROUP-IIIA NITRIDE LAYER
    Publication number: 20170372888
    Abstract: Problems associated with the mismatch between a silicon substrate and a group-IIIA nitride layer are addressed by employing a silicon substrate processed to have a surface comprising closely spaced tips extending from the surface, depositing a group-IIIB silicide layer on the tips, then depositing a group-IIIB nitride layer, and then depositing a group-IIIA nitride.
    Type: Application
    Filed: January 15, 2016
    Publication date: December 28, 2017
    Applicant: Siltronic AG
    Inventors: Sarad Bahadur THAPA, Maik HAEBERLEN, Marvin ZOELLNER, Thomas SCHROEDER
  • Method for monitoring the operational state of a surface inspection system for detecting defects on the surface of semiconductor wafers
    Patent number: 9835567
    Abstract: The operational state of a surface inspection system for detecting defects on the surface of semiconductor wafers is monitored by: providing a reference wafer having defects of a particular number, size, and density on an examination surface; conducting a reference inspection of the reference wafer and at least one control inspection of the reference wafer by the surface inspection system, the position and size of defects on the examination surface being measured; identifying defects which, because of their position, are regarded as common defects of the reference inspection and of the control inspection; for each common defect, determining a size difference obtained from comparing its size from the reference inspection and from the control inspection; and assessing the operational state of the surface inspection system on the basis of the size differences.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: December 5, 2017
    Assignee: SILTRONIC AG
    Inventor: Frank Laube
  • Apparatus and process for producing a crystal of semiconductor material
    Patent number: 9828693
    Abstract: A crystal of semiconductor material is produced in an apparatus having a crucible with a crucible bottom and a crucible wall, the crucible bottom having a top surface, an underside, and a multitude of openings disposed between the crucible wall and a center of the crucible bottom, and elevations disposed on the top surface and the underside of the crucible bottom; and an induction heating coil disposed below the crucible for melting semiconductor material and stabilizing a melt of semiconductor material covering a growing crystal of semiconductor material. The growth process comprises generating a bed of a semiconductor material feed on the top surface of the crucible bottom and melting semiconductor material on the bed using the induction heating coil.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: November 28, 2017
    Assignee: SILTRONIC AG
    Inventors: Georg Brenninger, Georg Raming
  • Apparatus and process for producing a single crystal of silicon
    Patent number: 9828692
    Abstract: An apparatus for producing a single crystal of silicon comprises a plate with a top side, an outer edge, and an inner edge, a central opening adjoining the inner edge, and a tube extending from the central opening to beneath the bottom side of the plate; a device for metering granular silicon onto the plate; a first induction heating coil above the plate, provided for melting of the granular silicon deposited; a second induction heating coil positioned beneath the plate, provided for stabilization of a melt of silicon, the melt being present upon a growing single crystal of silicon. The top side of the plate consists of ceramic material and has elevations, the distance between the elevations in a radial direction being not less than 2 mm and not more than 15 mm.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: November 28, 2017
    Assignee: SILTRONIC AG
    Inventors: Georg Brenninger, Waldemar Stein, Maik Haeberlen
  • Ultrasonic cleaning method and ultrasonic cleaning apparatus
    Patent number: 9773688
    Abstract: An ultrasonic cleaning method for cleaning an object in a liquid in which a gas is dissolved includes preparing the liquid in which the gas is dissolved and stirring the liquid while irradiating the liquid with the ultrasonic waves so as to realize a state where bubbles containing the gas dissolved in the liquid continue to be generated. The object is cleaned in the state where the bubbles containing the gas continue to be generated.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: September 26, 2017
    Assignee: SILTRONIC AG
    Inventors: Teruo Haibara, Etsuko Kubo, Yoshihiro Mori, Masashi Uchibe
  • Method for manufacturing single-crystal silicon
    Patent number: 9702055
    Abstract: The success rate of multi-pulled single crystal growth by the Czochralski method is enhanced by the use of a melt crucible having an amount of barium on an inner surface thereof which varies inversely with the diameter of the crucible. At least one single crystal is separated from the melt by a free span method.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: July 11, 2017
    Assignee: SILTRONIC AG
    Inventors: Hideo Kato, Shinichi Kyufu
  • Epitaxial wafer and a method of manufacturing thereof
    Patent number: 9691632
    Abstract: An epitaxial wafer comprises a silicon substrate wafer having first and second sides, and a silicon epitaxial layer deposited on the first side, and optionally one or more additional epitaxial layers on top of the silicon epitaxial layer, at least one of the silicon epitaxial layer or at least one of the one or more additional epitaxial layers being doped with nitrogen at a concentration of 1×1016 atoms/cm3 or more and 1×1020 atoms/cm3 or less. The epitaxial wafer is produced by depositing the silicon epitaxial layer and/or at least one of the one or more additional epitaxial layers, at a deposition temperature of 940° C. or less through chemical vapor deposition in the presence of a deposition gas atmosphere containing one or more silicon precursor compounds and one or more nitrogen precursor compounds.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: June 27, 2017
    Assignees: Siltronic AG, Intel Corporation
    Inventors: Peter Storck, Norbert Werner, Martin Vorderwestner, Peter Tolchinsky, Irwin Yablok
  • Method for recharging raw material polycrystalline silicon
    Patent number: 9670593
    Abstract: A method for recharging raw material polycrystalline silicon which enables large chunks of polycrystalline silicon to be recharged to a CZ ingot growth process while preventing the CZ crucible from being damaged and restricting a decline of the dislocation free rate and the quality of the grown ingot. Polycrystalline silicon chunks are recharged by first forming cushioning layer silicon of smaller chunks. The cushioning layer of polycrystalline silicon chunks are deposited on a surface of the residual silicon melt in a crucible. Subsequently, large-sized polycrystalline silicon chunks are introduced onto the cushioning layer, the cushioning layer cushioning the impact due to dropping of the large-sized polycrystalline silicon chunks.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: June 6, 2017
    Assignee: SILTRONIC AG
    Inventors: Hideo Kato, Satoko Yoshimura, Takeshi Ninomiya