Patents Assigned to Siltronic AG
  • Patent number: 8974267
    Abstract: An insert carrier is configured to receive at least one semiconductor wafer for double-side processing of the wafer between two working disks of a lapping, grinding or polishing process. The insert carrier includes a core of a first material that has a first surface and a second surface, and at least one opening configured to receive a semiconductor wafer. A coating at least partially covers the first and second surfaces of the core. The coating includes a surface remote from the core that includes a structuring including elevations and depressions. A correlation length of the elevations and depressions is in a range of 0.5 mm to 25 mm and an aspect ratio of the structuring is in a range of 0.0004 to 0.4.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: March 10, 2015
    Assignee: Siltronic AG
    Inventors: Georg Pietsch, Michael Kerstan
  • Patent number: 8968054
    Abstract: A method for cooling a cylindrical workpiece during wire sawing includes applying a liquid coolant to a surface of the workpiece. The workpiece is made of semiconductor material having a surface including two end faces and a lateral face. The method includes sawing the workpiece with a wire saw including a wire web having wire sections arranged in parallel by penetrating the wire sections into the workpiece by an oppositely directed relative movement of the wire sections and the workpiece. Wipers are disposed so as to bear on the surface of the workpiece. The temperature of the workpiece is controlled during the wire sawing using a liquid coolant applied onto the workpiece above the wipers so as to remove the liquid coolant with the wipers bearing on the workpiece surface.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: March 3, 2015
    Assignee: Siltronic AG
    Inventors: Peter Wiesner, Anton Huber
  • Patent number: 8961685
    Abstract: P-type silicon single crystals from which wafers having high resistivity, good radial uniformity of resistivity and less variation in resistivity can be obtained, are manufactured by the Czochralski method from an initial silicon melt in which boron and phosphorus are present, the boron concentration is not higher than 4E14 atoms/cm3 and the ratio of the phosphorus concentration to the boron concentration is not lower than 0.42 and not higher than 0.50.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: February 24, 2015
    Assignee: Siltronic AG
    Inventors: Katsuhiko Nakai, Masamichi Ohkubo
  • Publication number: 20150040820
    Abstract: The success rate of multi-pulled single crystal growth by the Czochralski method is enhanced by the use of a melt crucible having an amount of barium on an inner surface thereof which varies inversely with the diameter of the crucible. At least one single crystal is separated from the melt by a free span method.
    Type: Application
    Filed: July 10, 2012
    Publication date: February 12, 2015
    Applicant: SILTRONIC AG
    Inventors: Hideo Kato, Shinichi Kyufu
  • Patent number: 8911281
    Abstract: A method for trimming two working layers including bonded abrasive applied on mutually facing sides of an upper and a lower working disk of a grinding apparatus configured for simultaneous double-side processing of flat workpiece includes providing the grinding apparatus including the upper and lower working disks and providing at least one carrier including an outer toothing. The upper and lower working disks are rotated. The carrier is moved between the rotating working disks using a rolling apparatus and the outer toothing on cycloidal paths relative to working layers of the working disks. Loose abrasives are added to a working gap formed between the working layers. A carrier, without workpieces inserted therein, is moved in the working gap so as to effect material removal from the working layers.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: December 16, 2014
    Assignee: Siltronic AG
    Inventors: Georg Pietsch, Michael Kerstan
  • Publication number: 20140360425
    Abstract: The diameter of a single crystal is controlled to a set point diameter during pulling of the single crystal from a melt contained in a crucible and which forms a meniscus at a phase boundary on the edge of the single crystal, the meniscus having a height which corresponds to the distance between the phase boundary and a level of the surface of the melt outside the meniscus, comprising repeatedly: determining the diameter of a bright ring on the meniscus; calculating a diameter of the single crystal while taking into account the diameter of the bright ring and the dependency of the diameter of the bright ring on the height of the meniscus and on the diameter of the single crystal itself; and calculating at least one manipulated variable for controlling the diameter of the single crystal on the basis of the difference between the calculated diameter of the single crystal and the set point diameter of the single crystal.
    Type: Application
    Filed: May 23, 2014
    Publication date: December 11, 2014
    Applicant: SILTRONIC AG
    Inventor: Thomas SCHROECK
  • Patent number: 8906157
    Abstract: Single crystal composed of silicon with a section having a diameter that remains constant, are pulled by a method wherein the single crystal is pulled with a predefined pulling rate vp having the units [mm/min]; and the diameter of the single crystal in the section having a diameter that remains constant is regulated to the predefined diameter by regulating the heating power of a first heating source which supplies heat to the single crystal and to a region of the melt that adjoins the single crystal and is arranged above the melt, such that diameter fluctuations are corrected with a period duration T that is not longer than (2·18 mm)/vp.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: December 9, 2014
    Assignee: Siltronic AG
    Inventors: Thomas Schroeck, Wilfried von Ammon, Claus Kropshofer
  • Patent number: 8882565
    Abstract: A method of polishing a semiconductor wafer includes applying a polishing pad to the semiconductor wafer so as to subject the semiconductor wafer to a polishing process and supplying an aqueous polishing agent solution between the polishing pad and the semiconductor wafer. The polishing pad includes fixedly bonded abrasives of SiO2 with an average grain size in a range of 0.1 to 1.0 ?m. The aqueous polishing agent solution comprising an alkaline component, being free of solid materials and having a variable pH value in a range of 11 to 13.5. The aqueous polishing agent solution is maintained at a pH value of less than 13 during the polishing process and the pH value of the aqueous polishing agent solution is increased to a range of 13 to 13.5 so as to end the polishing process.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: November 11, 2014
    Assignee: Siltronic AG
    Inventors: Juergen Schwandner, Roland Koppert
  • Publication number: 20140326173
    Abstract: Single crystal silicon ingots are grown by the multi-pulling method in a single crucible with minimization of dislocations by incorporating barium as a quartz crystallization inhibitor in amounts proportional to the diameter of the Czochralski crucible in which the crystal is grown. In at least one of the crystal pulling steps, a magnetic field is applied.
    Type: Application
    Filed: May 15, 2012
    Publication date: November 6, 2014
    Applicant: SILTRONIC AG
    Inventors: Hideo Kato, Shinichi Kyufu, Masamichi Ohkubo
  • Patent number: 8872307
    Abstract: Silicon wafers having a resistivity >6 ?cm and axially uniform resistivity are grown by the Czochralski method from a melt containing boron as the main dopant, an n-type first sub-dopant with a segregation coefficient lower than boron, and a p-type second sub-dopant with a segregation coefficient lower than the first sub-dopant.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: October 28, 2014
    Assignee: Siltronic AG
    Inventor: Katsuhiko Nakai
  • Publication number: 20140308878
    Abstract: A method of polishing a semiconductor wafer includes simultaneous double-side polishing the wafer in a gap of a polishing device between a lower polishing plate covered with a lower polishing pad and upper polishing plate covered with an upper polishing pad while supplying a polishing agent. A first of the upper and lower polishing pads is dressed using a dressing tool. The dressing tool is mounted in the gap so that it extends from the inner edge to the outer edge of the first polishing pad. The distance between the dressing tool and a second of the upper and lower polishing pads at the inner edge of the second polishing pad differs from a corresponding distance at the outer edge of the second polishing pad. After the dressing, the at least one semiconductor wafer in the gap is polished.
    Type: Application
    Filed: April 10, 2014
    Publication date: October 16, 2014
    Applicant: Siltronic AG
    Inventors: Rainer Baumann, Johannes Staudhammer, Alexander Heilmaier, Leszek Mistur, Klaus Roettger
  • Patent number: 8851958
    Abstract: A method for simultaneous double-side material-removing processing of at least three workpieces includes disposing the workpieces in a working gap between rotating upper and lower working disks of a double-side processing apparatus. The workpieces lie in freely movable fashion in respective openings in a guide cage and are moved under pressure in the working gap using the guide cage. Upon attaining a preselected target thickness of the workpieces, a deceleration process is initiated that includes reducing an angular velocity ?i(t) of a respective drive i of each of the upper working disk, lower working disk and guide cage to a standstill. The reducing is carried out such that ratios of the angular velocities ?i(t) with respect to one another as a function of time t deviate by no more than 10% from initial ratios of the angular velocities ?i(t) corresponding to when the preselected target thickness was attained.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: October 7, 2014
    Assignee: Siltronic AG
    Inventor: Georg Pietsch
  • Patent number: 8844511
    Abstract: A method for slicing a plurality of wafers from a crystal includes providing a crystal of semiconductor material having a longitudinal axis, a cross section and at least one pulling edge. The crystal is fixed on a table and guided through a wire gang defined by sawing wire so as to form the wafers. The guiding is provided by a relative movement between the table and the wire gang such that entry sawing or exit sawing using the sawing wire occurs in a vicinity of the at least one pulling edge of the crystal.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: September 30, 2014
    Assignee: Siltronic AG
    Inventors: Maximilian Kaeser, Albert Blank
  • Publication number: 20140287656
    Abstract: A method for polishing at least one semiconductor wafer while supplying a polishing agent includes performing a first simultaneous double-side polishing of the front side and the back side of the at least one semiconductor wafer with first upper and lower polishing pads, edge-notch polishing the surface of the at least one semiconductor wafer, performing a second simultaneous double-side polishing of the front side and the back side of the at least on semiconductor wafer with second upper and lower polishing pads, where the upper and lower polishing pads for the first simultaneous double-side polishing are harder and less compressible than the upper and lower polishing pads for the second simultaneous double-side polishing and performing single-side polishing of the front side of the at least one semiconductor wafer.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 25, 2014
    Applicant: Siltronic AG
    Inventor: Juergen Schwandner
  • Publication number: 20140264776
    Abstract: A semiconductor wafer contains the following layers in the given order: a monocrystalline substrate wafer (1) consisting predominantly of silicon and having a (111) surface orientation, a monocrystalline layer (3) of Sc2O3 having a (111) surface orientation, a monocrystalline layer (4) of ScN having a (111) surface orientation, and a monocrystalline layer (6) of AlzGa1-zN with 0?z?1 having a (0001) surface orientation, the semiconductor wafers are produced by appropriate deposition of the respective layers.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 18, 2014
    Applicant: Siltronic AG
    Inventors: Sarad Bahadur Thapa, Thomas Schroeder, Lidia Tarnawska
  • Patent number: 8835284
    Abstract: Annealed wafers having reduced residual voids after annealing and reduced deterioration of TDDB characteristics of an oxide film formed on the annealed wafer, while extending the range of nitrogen concentration contained in a silicon single crystal, are prepared by a method wherein crystal pulling conditions are controlled such that a ratio V/G between a crystal pulling rate V and an average axial temperature gradient G is ?0.9×(V/G)crit and ?2.5×(V/G)crit, and hydrogen partial pressure is ?3 Pa and ?40 Pa. The silicon single crystal has a nitrogen concentration of >5×1014 atoms/cm3 and ?6×1015atoms/cm3, a carbon concentration of ?1×1015 atoms/cm3 and ?9×1015 atoms/cm3, and heat treatment is performed in a noble gas atmosphere having an impurity concentration of ?5 ppma, or in a non-oxidizing atmosphere.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: September 16, 2014
    Assignee: Siltronic AG
    Inventors: Katsuhiko Nakai, Masamichi Ohkubo
  • Patent number: 8834627
    Abstract: Silicon single crystals are grown by a method of remelting silicon granules, by crystallizing a conically extended section of the single crystal with the aid of an induction heating coil arranged below a rotating plate composed of silicon; feeding inductively melted silicon through a conical tube in the plate, the tube enclosing a central opening of the plate and extending below the plate, to a melt situated on the conically extended section of the single crystal in contact with a tube end of the conical tube, wherein by means of the induction heating coil below the plate, sufficient energy is provided to ensure that the external diameter of the tube end is not smaller than 15 mm as long as the conically extended section of the single crystal has a diameter of 15 to 30 mm.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: September 16, 2014
    Assignee: Siltronic AG
    Inventors: Wilfried von Ammon, Ludwig Altmannshofer, Martin Wasner
  • Patent number: 8829532
    Abstract: Semiconductor layer structure and a method for producing a structure are provided, including a substrate made of semiconductor material, on which a layer made of a second semiconductor material is situated, furthermore a region (3) enriched with impurity atoms, which region is situated either in layer (2) or at a specific depth below the interface between layer (2) and substrate (1), additionally a layer (4) within the region (3) enriched with impurity atoms, which layer comprises cavities produced by ion implantation, furthermore at least one epitaxial layer (6) applied to layer (2) and also a defect region (5) comprising dislocations and stacking faults within the layer (4) comprising cavities, the at least one epitaxial layer (6) being largely crack-free, and a residual strain of the at least one epitaxial layer (6) being less than or equal to 1 GPa.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: September 9, 2014
    Assignee: Siltronic AG
    Inventors: Brian Murphy, Maik Häberlen, Jörg Lindner, Bernd Stritzker
  • Publication number: 20140235143
    Abstract: A method for conditioning polishing pads for the simultaneous double-side polishing of semiconductor wafer uses a double-side polishing device. The device has an annular lower polishing plate and an annular upper polishing plate, each covered with a polishing pad, as well as a rolling device for carrier disks. The method for conditioning polishing pads includes disposing at least one conditioning tool having external teeth and at least one spacer having external teeth in a working gap formed between the first and second polishing pad, where the thickness of at least one of the conditioning tools differs from the thickness of at least one of the spacers. At least one conditioning tool and one spacer are set, simultaneously, in a revolving movement about the axis of the rolling device and in rotation themselves so as to generate material abrasion of at least one of the polishing pads.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 21, 2014
    Applicant: Siltronic AG
    Inventor: Johannes Staudhammer
  • Patent number: RE45238
    Abstract: A silicon wafer in which both occurrences of slip dislocation and warpage are suppressed in device manufacturing processes is a silicon wafer having BMDs having an octahedral shape, wherein BMDs located at a position below the silicon wafer surface to a depth of 20 ?m and having a diagonal length of 200 nm or more are present at a concentration of ?2×109/cm3, and BMDs located at a position below a depth ?50 ?m have a diagonal length of ?10 nm to ?50 nm and a concentration of ?1×1012/cm3.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: November 11, 2014
    Assignee: Siltronic AG
    Inventors: Masayuki Fukuda, Katsuhiko Nakai