Patents Assigned to Siltronic AG
  • Publication number: 20130093058
    Abstract: Silicon wafers having a resistivity >6 ?cm and axially uniform resistivity are grown by the Czochralski method from a melt containing boron as the main dopant, an n-type first sub-dopant with a segregation coefficient lower than boron, and a p-type second sub-dopant with a segregation coefficient lower than the first sub-dopant.
    Type: Application
    Filed: September 12, 2012
    Publication date: April 18, 2013
    Applicant: SILTRONIC AG
    Inventor: Katsuhiko Nakai
  • Patent number: 8408221
    Abstract: A micro-bubble generating device is provided with a micro-bubble generating mechanism and a leading conduit provided with a widening section and a tube part, the widening section and the tube part in communication with each other in the leading conduit. The widening section has a hollow shape which has an axis Z as a central axis, and has base surfaces and a peripheral surface, and communicates with a nozzle of the micro-bubble-generating mechanism via one base surface of the widening section, and communicates with the tube part via the other base surface. The cross section orthogonal to a flow axis Z of the micro-bubbles of the widening section is larger than the cross section orthogonal to the flow axis Z of the tube part.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: April 2, 2013
    Assignee: Siltronic AG
    Inventor: Teruo Haibara
  • Patent number: 8409992
    Abstract: A polished semiconductor wafer of high flatness is produced by the following ordered steps: slicing a semiconductor wafer from a rod composed of semiconductor material, material-removal processing of at least one side of the semiconductor wafer, and polishing of at least one side of the semiconductor wafer, wherein the semiconductor wafer has, after the material-removing processing and before the polishing on at least one side to be polished, along its margin, a ring-shaped local elevation having a maximum height of at least 0.1 ?m, wherein the local elevation reaches its maximum height within a 10 mm wide ring lying at the edge of the semiconductor wafer.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: April 2, 2013
    Assignee: Siltronic AG
    Inventors: Bertram Moeckel, Helmut Franke
  • Publication number: 20130078743
    Abstract: A layer is deposited onto a semiconductor wafer by CVD in a process chamber having upper and lower covers, wherein the wafer front side temperature is measured; the wafer is heated to deposition temperature; the temperature of the upper process chamber cover is controlled to a target temperature by measuring the temperature of the center of the outer surface of the upper cover as the value of a controlled variable of an upper cover temperature control loop; a gas flow rate of process gas for depositing the layer is set; and a layer is deposited on the heated wafer front side during control of the upper cover temperature to the target temperature. A process chamber suitable therefor has a sensor for measuring the upper cover outer surface center temperature and a controller for controlling this temperature to a predetermined value.
    Type: Application
    Filed: September 5, 2012
    Publication date: March 28, 2013
    Applicant: SILTRONIC AG
    Inventor: Georg Brenninger
  • Publication number: 20130072093
    Abstract: A method for simultaneous double-side material-removing processing of at least three workpieces includes disposing the workpieces in a working gap between rotating upper and lower working disks of a double-side processing apparatus. The workpieces lie in freely movable fashion in respective openings in a guide cage and are moved under pressure in the working gap using the guide cage. Upon attaining a preselected target thickness of the workpieces, a deceleration process is initiated that includes reducing an angular velocity ?i(t) of a respective drive i of each of the upper working disk, lower working disk and guide cage to a standstill. The reducing is carried out such that ratios of the angular velocities ?i(t) with respect to one another as a function of time t deviate by no more than 10% from initial ratios of the angular velocities ?i(t) corresponding to when the preselected target thickness was attained.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 21, 2013
    Applicant: SILTRONIC AG
    Inventor: Georg Pietsch
  • Publication number: 20130072091
    Abstract: A method of simultaneous double-side polishing of a front side and a rear side of at least one wafer composed of semiconductor material includes disposing each wafer in a respective suitably dimensioned cutout in a carrier plate. The at least one wafer is polished on the front side and on the rear side between an upper polishing plate covered with a first polishing pad and a lower polishing plate covered with a second polishing pad while supplying a polishing agent. A respective surface of each of the first and second polishing pads is interrupted by at least one respective channel-shaped depression running spirally from a center to an edge of the respective pad.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 21, 2013
    Applicant: SILTRONIC AG
    Inventor: Juergen Schwandner
  • Publication number: 20130068262
    Abstract: Semiconductor wafers are treated in a liquid container filled at least partly with a solution containing hydrogen fluoride, such that surface oxide dissolves, are transported out of the solution along a transport direction and dried, and are then treated with an ozone-containing gas to oxidize the surface of the semiconductor wafer, wherein part of the semiconductor wafer surface comes into contact with the ozone-containing gas while another part of the surface is still in contact with the solution, and wherein the solution and the ozone-containing gas are spatially separated such that they do not come into contact with one another.
    Type: Application
    Filed: November 13, 2012
    Publication date: March 21, 2013
    Applicant: SILTRONIC AG
    Inventor: SILTRONIC AG
  • Patent number: 8398766
    Abstract: Semiconductor wafers composed of monocrystalline silicon and doped with nitrogen contain an OSF region and a Pv region, wherein the OSF region extends from the center radially toward the edge of the wafer as far as the Pv region; the wafer has an OSF density of less than 10 cm?2, a BMD density in the bulk of at least 3.5×108 cm?3, and a radial distribution of the BMD density with a fluctuation range BMDmax/BMDmin of not more than 3. The wafers are produced by controlling initial nitrogen content and maintaining oxygen within a narrow window, followed by a heat treatment.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: March 19, 2013
    Assignee: Siltronic AG
    Inventors: Timo Mueller, Gudrun Kissinger, Walter Heuwieser, Martin Weber
  • Patent number: 8398878
    Abstract: Semiconductor wafers are polished by a material-removing polishing process A, on both sides of the wafer, using an abrasive-free polishing pad, and a polishing agent which contains abrasive; and a material-removing polishing process B, on at least one side of the wafer, using a polishing pad with a microstructured surface containing no materials which contact the wafer which are harder than the semiconductor material, and a polishing agent is added which has a pH? to 10 and contains no substances with abrasive action. Preferred is a method for producing a semiconductor wafer, comprising the following ordered steps: separating a semiconductor single crystal into wafers; simultaneously processing both sides of the wafer by chip-removing processing; polishing the wafer, comprising a polishing process A and a polishing process B; and CMP of one side of the wafer, removing <1 ?m.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: March 19, 2013
    Assignee: Siltronic AG
    Inventor: Georg Pietsch
  • Publication number: 20130061842
    Abstract: Wire spools used for multiple wire saws for slicing one or more wafers from a workpiece composed of semiconductor material using a wire web including parallel wire sections coated with bonded abrasive grain. The wire spools include a first wire spool configured as a dispensing spool and a second wire spool configured as a receiver spool. A sawing wire coated with bonded abrasive grain runs from the first wire spool via at least one deflection roll to the wire web and from the wire web via at least one deflection roll to the second wire spool. The sawing wire enters into guide grooves of the deflection rolls at an alignment angle ?1 and exits the guide grooves of the deflection rolls at an alignment angle ?2. The sawing wire has a single layer winding on each of the first and second wire spools.
    Type: Application
    Filed: August 27, 2012
    Publication date: March 14, 2013
    Applicant: SILTRONIC AG
    Inventors: Joachim Junge, Joerg Moser
  • Patent number: 8395164
    Abstract: Silicon carbide substrate wafers are prepared by transferring a monocrystalline silicon layer from a donor wafer onto a handle wafer, the silicon layer being implanted with carbon and annealed to form a monocrystalline SiC layer prior to or after transfer of the silicon layer.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: March 12, 2013
    Assignee: Siltronic AG
    Inventors: Brian Murphy, Reinhold Wahlich
  • Patent number: 8389409
    Abstract: Semiconductor wafers are produced by a process of: a) providing a semiconductor wafer by cutting a silicon ingot into wafers; b) rounding the edge of the wafer, so that the wafer comprises plane surfaces on the frontside and backside and rounded oblique surfaces in the edge region; c) polishing the frontside and backside of the wafer, the frontside being polished by chemical-mechanical polishing using a polishing pad which is free of abrasive fixed in the polishing pad; backside polishing being carried out in three steps, using a polishing pad containing fixed abrasive which is pressed onto the backside of the wafer, a polishing agent free of solids introduced between the polishing pad and the backside of the wafer in the first step, a polishing agent containing abrasive being introduced in the second and third steps, a polishing pressure of 8-15 psi in the first and second steps being reduced to 0.5-5 psi in the third step.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: March 5, 2013
    Assignee: Siltronic AG
    Inventor: Juergen Schwandner
  • Patent number: 8388411
    Abstract: A method for polishing the edge of a semiconductor wafer comprises (a) providing a semiconductor wafer which has been polished on its side surfaces and which has a rounded edge; (b) polishing the edge of the wafer by fixing the semiconductor wafer on a centrally rotating chuck, delivering the wafer to a centrally rotating polishing drum, which is inclined with respect to the chuck and to which a polishing pad containing fixedly bonded abrasives is applied, and pressing semiconductor wafer and polishing drum onto one another while a polishing agent solution containing no solids is continuously supplied.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: March 5, 2013
    Assignee: Siltronic AG
    Inventor: Juergen Schwandner
  • Patent number: 8383495
    Abstract: Semiconductor layer structure and a method for producing a structure are provided, including a substrate made of semiconductor material, on which a layer made of a second semiconductor material is situated, furthermore a region (3) enriched with impurity atoms, which region is situated either in layer (2) or at a specific depth below the interface between layer (2) and substrate (1), additionally a layer (4) within the region (3) enriched with impurity atoms, which layer comprises cavities produced by ion implantation, furthermore at least one epitaxial layer (6) applied to layer (2) and also a defect region (5) comprising dislocations and stacking faults within the layer (4) comprising cavities, the at least one epitaxial layer (6) being largely crack-free, and a residual strain of the at least one epitaxial layer (6) being less than or equal to 1 GPa.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: February 26, 2013
    Assignee: Siltronic AG
    Inventors: Brian Murphy, Maik Haeberlen, Joerg Lindner, Bernd Stritzker
  • Patent number: 8382894
    Abstract: Silicon wafers wherein slip dislocations and warpages during device production are suppressed, contain BMDs with an octahedral shape, and of BMDs at a depth greater than 50 ?m from the surface of the wafer, the density of BMDs with diagonal size of 10 nm to 50 nm is ?1×1012/cm3, and the density of BSFs is ?1×108/cm3. The present silicon wafers preferably have an interstitial oxygen concentration of 4×1017 atoms/cm3 to 6×1017 atoms/cm3, and a density of BMDs with diagonal size of ?200 nm of not more than 1×107/cm3.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: February 26, 2013
    Assignee: Siltronic AG
    Inventors: Katsuhiko Nakai, Masayuki Fukuda
  • Patent number: 8377219
    Abstract: A method for cleaning a semiconductor wafer composed of silicon directly after a process of chemical mechanical polishing of the semiconductor wafer includes transferring the semiconductor wafer from a polishing plate to a first cleaning module and spraying both side surfaces of the semiconductor wafer with water at a pressure no greater than 1000 Pa at least once while transferring the semiconductor wafer. The semiconductor wafer is then cleaned between rotating rollers with water. The side surfaces of the semiconductor wafer are sprayed with an aqueous solution containing hydrogen fluoride and a surfactant at a pressure no greater than 70,000 Pa. Subsequently, the side surfaces are sprayed with water at a pressure no greater than 20,000 Pa. The wafer is then dipped into an aqueous alkaline cleaning solution, and then cleaned between rotating rollers with a supply of water. The semiconductor wafer is then sprayed with water and dried.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: February 19, 2013
    Assignee: Siltronic AG
    Inventor: Reinhold Lanz
  • Patent number: 8376811
    Abstract: Semiconductor wafers are double sided polished by a method of polishing a frontside of the wafer in a first step with a polishing pad with fixed abrasive and simultaneously polishing a backside of the wafer with a polishing pad containing no abrasive, but during which an abrasive polishing agent is introduced between the polishing pad and the backside of the wafer, inverting the wafer, and then in a second step polishing the backside of the wafer with a polishing pad containing fixed abrasive and simultaneously polishing the frontside of the wafer with a polishing pad containing no fixed abrasive, a polishing agent containing abrasive being introduced between the polishing pad and the frontside of the semiconductor wafer.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: February 19, 2013
    Assignee: Siltronic AG
    Inventor: Juergen Schwandner
  • Patent number: 8376810
    Abstract: A semiconductor wafer processed on both sides simultaneously, the wafer lying in freely movable fashion in a cutout in one of a plurality of carriers that rotate by means of a rolling apparatus, and one thereby being moved on a cycloidal trajectory, the semiconductor wafer being processed in material-removing fashion between two rotating ring-shaped working disks, wherein each working disk comprises a working layer comprising abrasive material, and wherein an alkaline medium comprising no abrasive material is supplied during the processing.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: February 19, 2013
    Assignee: Siltronic AG
    Inventor: Juergen Schwandner
  • Patent number: 8372213
    Abstract: Semiconductor wafers are treated in a liquid container filled at least partly with a solution containing hydrogen fluoride, such that surface oxide dissolves, are transported out of the solution along a transport direction and dried, and are then treated with an ozone-containing gas to oxidize the surface of the semiconductor wafer, wherein part of the semiconductor wafer surface comes into contact with the ozone-containing gas while another part of the surface is still in contact with the solution, and wherein the solution and the ozone-containing gas are spatially separated such that they do not come into contact with one another.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: February 12, 2013
    Assignee: Siltronic AG
    Inventors: Guenter Schwab, Diego Feijoo, Thomas Buschhardt, Hans-Joachim Luthe, Franz Sollinger
  • Patent number: 8372298
    Abstract: Epitaxially coated silicon wafers, are coated individually in an epitaxy reactor by a procedure in which a silicon wafer on a susceptor in the epitaxy reactor, is pretreated in a first step with a hydrogen flow rate of 1-100 slm and in a second step with hydrogen and an etching medium at a hydrogen flow rate of 1-100 slm, and an etching medium flow rate of 0.5-1.5 slm, at an average temperature of 950-1050° C., and is subsequently coated epitaxially, wherein, during the second pretreatment step, the power of heating elements is regulated such that there is a temperature difference of 5-30° C. between a radially symmetrical central region of the silicon wafer and an outer region of the silicon outside the central region.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: February 12, 2013
    Assignee: Siltronic AG
    Inventor: Joerg Haberecht