Abstract: A semiconductor device includes: a gate trench formed into a semiconductor substrate; a gate dielectric layer formed in the gate trench to cover an inside surface of the gate trench; and a gate electrode disposed over the gate dielectric layer to fill the gate trench, wherein the gate electrode includes: second crystal grains formed in the gate trench; and first crystal grains disposed between the second crystal grains and the gate dielectric layer and having a smaller crystal grain size than the second crystal grains.

Abstract: A semiconductor device includes: a first stacked structure including a first lower dielectric layer, a first horizontal gate structure, and a first upper dielectric layer stacked vertically; a second stacked structure including a second lower dielectric layer, a second horizontal gate structure, and a second upper dielectric layer stacked vertically, and having a first side facing a first side of the first stacked structure; a first channel layer formed on the first side of the first stacked structure; a second channel layer formed on the first side of the second stacked structure; a lower electrode layer commonly coupled to lower ends of the first and second channel layers between the first and second stacked structures; a first upper electrode layer coupled to an upper end of the first channel layer; and a second upper electrode layer coupled to an upper end of the second channel layer.

Abstract: An image sensing device includes a semiconductor substrate, a photoelectric conversion region structured to generate charge carriers from incident light and capture the charge carriers using an electric potential difference caused by a demodulation control signal applied to the photoelectric conversion region, and a circuit region disposed adjacent to the photoelectric conversion region, the circuit region including a plurality of pixel transistors that generate and output a pixel signal corresponding to the charge carriers captured by the photoelectric conversion region. The circuit region includes a first well region formed to have a first length in a first direction, and a second well region formed below the first well region such that a lower end of the first well region is in contact with an upper end of the second well region, and formed to have a second length shorter than the first length in the first direction.

Abstract: A semiconductor memory device and methods of manufacturing and operating the same are set forth. The semiconductor memory device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which may be alternately stacked on a substrate, and a plurality of channel structures penetrating the stack structure in a vertical direction. Each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, each of which vertically extends toward the substrate.

Abstract: A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.

Abstract: A three-dimensional memory device includes a lower stack and an upper stack stacked one on the other, and each including a plurality of word lines which are stacked alternately with a plurality of interlayer dielectric layers, wherein each of the lower stack and the upper stack includes a first cell part, a second cell part, a coupling part which couples the first cell part and the second cell part, and a staircase part which extends parallel to the coupling part from the first cell part and in which pad areas of the word lines are disposed in a stepwise manner, and wherein the coupling part of the upper stack is disposed to overlap with the staircase part of the lower stack, and the staircase part of the upper stack is disposed to overlap with the coupling part of the lower stack.

Abstract: A memory apparatus includes an address decoding circuit configured to output a test redundancy address based on an address that is transmitted from a memory controller; and a redundancy address check circuit configured to determine whether the test redundancy address is replacing a failed address, in order to perform an ECC test operation by using the test redundancy address.

Abstract: Disclosed are a data processing system comprising: a memory system for providing a host with a memory map segment including map pieces; and the host for storing the memory map segment as a host map segment and converting a logical address into a physical address using the host map segment. The memory system stores changed map pieces in a map cache, inserts the changed map pieces in a response to a first command, and provides the host with the response. The host updates the host map segment based on the changed map pieces. When a read command includes a logical address and a physical address, the memory system accesses a memory device using the physical address of the read command according to whether the logical address of the read command is stored in the map cache.

Abstract: A memory system includes a host circuit and a memory circuit. The host circuit controls a bandwidth of a command-address signal based on data driving cycle information. The memory circuit performs an input/output operation based on the command-address signal.

Abstract: A memory controller and a method of operating the same. The memory controller which increases the number of read commands to be performed during a suspend period may include a command generator configured to receive a request from a host and generate a command corresponding to the request, a command queue configured to store the generated command, a command controller configured to control the command queue so that the command stored in the command queue is output to the memory device, and a suspension controller configured to, when a read request is input from the host while the memory device is performing an operation, determine a delay amount of time based on a number of read commands stored in the command queue and provide a suspend command that instructs suspension of performance of the operation to the memory device after the delay amount of time has elapsed.

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device includes a transaction layer generating a transaction packet for transmission of a transaction, a data link layer generating a link packet including a protection code and a sequence number for the transaction packet and a link packet including a sequence number on the basis of the transaction packet, a physical layer generating a physical packet on the basis of the link packet and sequentially outputting the physical packet, a link training module performing negotiation for a link coupled through the physical layer and maintaining data information based on whether a link down occurring when the negotiation for the link is not performed is requested by a host or not, and a PCIe register storing information about the transaction layer, the data link layer, the physical layer, and the link training module.

Abstract: A memory system includes: a memory device suitable for providing row-hammer data to set refresh rates for adjacent word lines of a target word line, and performing a target refresh operation on one or more word lines corresponding to a first row-hammer address according to a first target refresh command; and a memory controller suitable for generating a plurality of sampling addresses by sampling an active address, generating a plurality of counting values by comparing the sampling addresses with the active address, calculating a plurality of adjacent addresses corresponding to the sampling addresses based on the counting values and the row-hammer data, and providing the adjacent addresses as the first row-hammer address with the first target refresh command.

Abstract: A buffer circuit includes a power control circuit, an inverting circuit, and a voltage adjustment circuit. The power control circuit is configured to provide voltages based on an input signal and a mode signal, and the inverting circuit is configured to receive and invert the voltages to generate an output signal. The voltage adjustment circuit is configured to adjust voltage levels based on the mode signal and the output signal.

Abstract: A semiconductor memory device includes a channel layer coupled to a bit line, a cell string located along a first side portion of the channel layer, and an auxiliary string located along a second side portion of the same channel layer.

Abstract: An image processing device including: a decision pixel manager for setting a decision area for a defect candidate pixel, and determining a first decision pixel and a second decision pixel, based on first phase information of pixels included in the decision area with respect to a first modulation frequency of a sensing light source among the pixels; a target pixel determiner for calculating a phase difference between the first decision pixel and the second decision pixel, based on second phase information of the pixels with respect to a second modulation frequency of the sensing light source, and determining the defect candidate pixel as a target pixel, corresponding to that the phase difference exceeds a predetermined reference value; and a phase corrector for changing a phase of the target pixel, based on the phase difference.

Abstract: A clock transfer circuit includes a first stage circuit configured to produce an output signal that uses a second signaling technology from an input signal that uses a first signaling technology; and a second stage circuit configured to produce a clock signal by delaying the output signal; wherein the first stage circuit includes a semiconductor device configured to compensate for delay fluctuation caused by fluctuation of power supply voltage between a first power source and a second power source.

Abstract: Provided is a semiconductor memory device and method of fabricating the semiconductor memory device. A semiconductor memory device includes a gate stack and a plurality of channel structures. The gate stack includes a plurality of stacked conductive patterns spaced apart from each other. The plurality of the channel structures is formed through the gate stack. Each of the channel structures includes a first channel pillar, a second channel pillar and a gate insulation layer. The first channel pillar is formed through the conductive patterns except for an uppermost conductive pattern. The second channel pillar is formed through the uppermost conductive pattern. The second channel pillar is configured to make contact with the first channel pillar. The gate insulation layer is interposed between the uppermost conductive pattern and the first and second channel pillars.

Abstract: A probe test card includes a substrate, a plurality of test needles, and a fixing layer. The substrate includes a first surface at which a trench is formed, and a second surface opposite to the first surface. The plurality of test needles is arranged in the trench. Each test needle includes a first end and a second end being opposite to the first end. The fixing layer is filled in the trench to fix the plurality of test needles in the trench, and a thickness of the fixing layer is same with a depth of the trench. The fixing layer comprises a ceramic powder. The first end of the test needle is non-removably fixed in the trench by the fixing layer and the second end of the test needle protrudes from the trench of the substrate to test a device under test (DUT).

Abstract: A method for fabricating a semiconductor device includes forming a stack structure including a horizontal recess over a substrate, forming a blocking layer lining the horizontal recess, forming an interface control layer including a dielectric barrier element and a conductive barrier element over the blocking layer, and forming a conductive layer over the interface control layer to fill the horizontal recess.

Abstract: A charge pump circuit is provided, comprising: a first charge pump having an input terminal for receiving a supply voltage and configured to boost the received supply voltage to provide at an output terminal of the first charge pump a first charge pump voltage; a second charge pump having an input terminal coupled to the output terminal of the first charge pump for receiving the first charge pump voltage and configured to boost the received first charge pump voltage to provide at an output terminal of the second charge pump a second charge pump voltage, and a voltage drop sensing device configured to detect drops in the first charge pump voltage and to deactivate second transistors of bypass units associated to the disabled charge pump stages when a drop in the first charge pump voltage is detected.