Patents Assigned to SK Hynix Inc.
  • ELECTRONIC DEVICE FOR PERFORMING SMART REFRESH OPERATION
    Publication number: 20240112718
    Abstract: An electronic device includes a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address; and a refresh control circuit configured to control a smart refresh operation on the target address.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 4, 2024
    Applicant: SK hynix Inc.
    Inventors: Jeong Jin HWANG, Sung Nyou YU, Duck Hwa HONG, Sang Ah HYUN, Soo Hwan KIM
  • Electronic device and method for manufacturing electronic device
    Patent number: 11950522
    Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: April 2, 2024
    Assignee: SK hynix Inc.
    Inventors: Myoung Sub Kim, Tae Hoon Kim, Beom Seok Lee, Seung Yun Lee, Hwan Jun Zang, Byung Jick Cho, Ji Sun Han
  • Image sensing device which outputs plural clock signals through respective plural output terminals
    Patent number: 11950008
    Abstract: Disclosed is an image sensing device including a first clock distributor suitable for receiving a first input dock signal through a first input terminal, and outputting a plurality of first output clock signals through a plurality of first output terminals, and a first conductive line coupled in common to the plurality of first output terminals.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: April 2, 2024
    Assignee: SK hynix Inc.
    Inventors: Jeong Eun Song, Min Seok Shin, Yu Jin Park, Sung Uk Seo, Sun Young Lee
  • Page buffer, memory device including the page buffer and operating method thereof
    Patent number: 11948645
    Abstract: An electronic device, and more particularly, a page buffer is provided. The page buffer includes a sensing node configured to sense a potential of a bit line coupled to a memory cell, a precharging circuit coupled to the sensing node and configured to precharge a potential of the sensing node to a first voltage during an evaluation operation on the memory cell, a discharging circuit coupled to the sensing node and configured to discharge the potential of the sensing node from the first voltage to a second voltage, and a latch circuit coupled to the discharging circuit and configured to store therein data sensed from the memory cell based on a result of comparing the potential of the sensing node with a reference voltage after the potential of the sensing node is discharged to the second voltage and a predetermined period elapses.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: April 2, 2024
    Assignee: SK hynix Inc.
    Inventors: Yeong Jo Mun, Dong Hun Kwak
  • Accumulator, operational logic circuit including accumulator, and processing-in-memory device including accumulator
    Patent number: 11948658
    Abstract: An accumulator includes an accumulating adder configured to add input data and latch data to output accumulation data, a selector configured to receive external data and the accumulation data, and output one of the external data and the accumulation data as selection data, and a latch circuit configured to latch the selection data output from the selector to transmit latched selection data into the accumulating adder as the latch data.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: April 2, 2024
    Assignee: SK hynix Inc.
    Inventor: Joon Hong Park
  • Nonvolatile memory device, operating method thereof, and memory system including the same
    Patent number: 11948643
    Abstract: A nonvolatile memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory regions coupled to a plurality of word lines. The plurality of memory regions include first and second memory regions coupled to upper and lower word lines, respectively. The control logic performs, after receiving first data and second data, a first program operation on the first memory region to store the first data and a second program operation on the second memory region to store the second data.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: April 2, 2024
    Assignee: SK hynix Inc.
    Inventors: Seunggu Ji, Yong Il Jung
  • Resistive memory device and operating method of the resistive memory device
    Patent number: 11948633
    Abstract: A resistive memory device includes: conductive layers and interlayer insulating layers, which are alternatively stacked; a vertical hole vertically penetrating the conductive layers and the interlayer insulating layers; a gate insulating layer disposed over an inner wall of the vertical hole; a charge trap layer disposed over an inner wall of the gate insulating layer; a channel layer disposed over an inner wall of the charge trap layer; and a variable resistance layer disposed over an inner wall of the channel layer.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: April 2, 2024
    Assignee: SK hynix Inc.
    Inventor: Jae Hyun Han
  • Parallel system to calculate low density parity check
    Patent number: 11949430
    Abstract: An LDPC encoding method and a system for error code detection. In the method and system, partial syndromes using a user portion and a low density parity check matrix are calculated, a parity portion of a codeword is calculated using the partial syndromes and using a quasi-cyclic matrix, the parity portion is generated by segment processing of the quasi-cyclic matrix, and the user portion and the parity portion are concatenated to complete the codeword.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: April 2, 2024
    Assignee: SK hynix Inc.
    Inventors: Fan Zhang, Haobo Wang, Hongwei Duan
  • Semiconductor device and manufacturing method of the semiconductor device
    Patent number: 11948993
    Abstract: The present technology provides a semiconductor device. The semiconductor device includes a stack including insulating patterns and conductive patterns stacked alternately with each other, a channel layer including a first channel portion protruding out of the stack and a second channel portion in the stack, and passing through the stack, and a conductive line surrounding the first channel portion, and the first channel portion includes metal silicide.
    Type: Grant
    Filed: March 8, 2023
    Date of Patent: April 2, 2024
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Memory device
    Patent number: 11950404
    Abstract: A memory device includes: a word line stack including word lines that are alternately stacked vertically over a substrate, and having an edge portion; at least one supporter extending vertically in a direction that the word lines are stacked and supporting the edge portion of the word line stack; contact plugs that are electrically connected to the word lines at the edge portion of the word line stack; and active layers positioned between the word lines, and horizontally oriented in a direction intersecting with the word lines.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: April 2, 2024
    Assignee: SK hynix Inc.
    Inventor: Seung Hwan Kim
  • Memory device
    Patent number: 11950406
    Abstract: A memory cell includes a bit line and a plate line that are spaced apart from each other and vertically oriented in a first direction; a transistor provided with an active region that is laterally oriented in a second direction crossing the bit line and includes a first active cylinder, a second active cylinder, and at least one channel portion oriented laterally between the first active cylinder and the second active cylinder; a word line extending in a third direction while surrounding the at least one channel portion of the active region; and a capacitor oriented laterally in the second direction between the active region and the plate line.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: April 2, 2024
    Assignee: SK hynix Inc.
    Inventor: Ki Hong Lee
  • METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    Publication number: 20240105652
    Abstract: A method of manufacturing a semiconductor device includes forming a first photoresist layer on a substrate and forming a second photoresist layer on the first photoresist layer. The method also includes forming a first dissolvable region having a first width in the first photoresist layer and a second dissolvable region having a second width different from the first width in the second photoresist layer by radiating exposure light to some parts of the second and first photoresist layer. The method further includes forming a second opening in the second photoresist layer and a first opening in the first photoresist layer by developing the second dissolvable region and the first dissolvable region. The method additionally includes forming a conductive bump that fills the first and second openings.
    Type: Application
    Filed: January 17, 2023
    Publication date: March 28, 2024
    Applicant: SK hynix Inc.
    Inventors: Dae Won KIM, Sung Kyu KIM
  • PACKAGING DEVICE INCLUDING BUMPS AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20240105656
    Abstract: A packaging device including bumps and a method of manufacturing the packaging device are presented. In the method of manufacturing a packaging device, a dielectric layer that covers a packaging base is formed and a lower layer is formed over a packaging base including first and second connecting pads. A plurality of dummy bumps that overlaps with the dielectric layer is formed. A sealing pattern that covers the dummy bumps, filling areas between the dummy bumps, is formed. A lower layer pattern in which the plurality of dummy bumps have been disposed is formed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern.
    Type: Application
    Filed: March 20, 2023
    Publication date: March 28, 2024
    Applicant: SK hynix Inc.
    Inventors: Jae Jun LEE, Jong Yeon KIM, Jong Hoon KIM, Ju Heon YANG, Mi Seon LEE
  • SEMICONDUCTOR MEMORY DEVICE INCLUDING A PLURALITY OF MEMORY BLOCKS AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20240107769
    Abstract: A semiconductor memory device may include a plurality of memory blocks and at least one insulation bridge. The plurality of the memory blocks may be defined by a plurality of slits parallel to each other. The at least one insulation bridge may be formed in at least one slit located on at least one side of a memory block of the plurality of memory blocks to support the adjacent memory blocks.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 28, 2024
    Applicant: SK hynix Inc.
    Inventor: Jung Shik JANG
  • Apparatus and method for checking an error of a non-volatile memory device in a memory system
    Patent number: 11941289
    Abstract: A memory system includes a memory device including plural memory groups, each memory group including plural non-volatile memory cells; and a controller configured to transmit a command to the memory device so that the memory device performs a data input/output operation within at least one memory group among the plural memory groups, receive a response for the command and a status data regarding the at least one memory group from the memory device, and determine whether the data input/output operation has succeeded or failed based on the response and the status data.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: March 26, 2024
    Assignee: SK hynix Inc.
    Inventors: Jung Ae Kim, Jee Yul Kim
  • Memory device related to performing a program operation on memory cells
    Patent number: 11942156
    Abstract: Provided herein is a memory device for performing a program operation on memory cells. The memory device include a plurality of memory cells configured to store data, a voltage generator configured to apply program voltages to a word line coupled to the plurality of memory cells during a program operation in which the plurality of memory cells are programmed to a plurality of program states, a cell speed determiner configured to determine a program speed of the plurality of memory cells depending on a number of pulses for the program voltages applied to the word line while the program operation is being performed, and a program manager configured to change a condition for remaining program operations depending on the program speed determined by the cell speed determiner.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: March 26, 2024
    Assignee: SK hynix Inc.
    Inventors: Hyeok Jun Choi, Hee Sik Park, Seung Geun Jeong
  • Memory system and operating method of memory system
    Patent number: 11941272
    Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, the memory system may, with respect to data stored in the memory device, write the data to a first target memory block or a second target memory block among the plurality of memory blocks according to whether a data type of the data is a read-intensive type or a write-intensive type.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: March 26, 2024
    Assignee: SK hynix Inc.
    Inventor: Jung Woo Kim
  • Semiconductor device including buried gate structure and method for fabricating the same
    Patent number: 11943912
    Abstract: A semiconductor device includes: a gate trench formed into a semiconductor substrate; a gate dielectric layer formed in the gate trench to cover an inside surface of the gate trench; and a gate electrode disposed over the gate dielectric layer to fill the gate trench, wherein the gate electrode includes: second crystal grains formed in the gate trench; and first crystal grains disposed between the second crystal grains and the gate dielectric layer and having a smaller crystal grain size than the second crystal grains.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: March 26, 2024
    Assignee: SK hynix Inc.
    Inventor: Dong-Soo Kim
  • Semiconductor device including internal transmission path and stacked semiconductor device using the same
    Patent number: 11942181
    Abstract: A semiconductor device comprises: a first or a second path configured to transmit a first signal which swings between a ground level and a first level, a third path configured to transmit a second signal which swings between the ground level and a second level lower than the first level, a transmitter configured to output received the first signal through the first or second path as the second signal to the third path, and initialize in response to an enable signal, and a receiver configured to output received the second signal through the third path as the first signal through the first or second path, determine level of the second signal through a reference level that is regulated according to a fed-back level of an output terminal thereof, and initialize in response to the enable signal.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: March 26, 2024
    Assignee: SK hynix Inc.
    Inventors: Jinhyung Lee, Myeong Jae Park, Su Hyun Oh, Chang Kwon Lee
  • Imaging device
    Patent number: 11943543
    Abstract: An imaging device may include an image sensing device including a plurality of pixels to detect incident light from a scene to generate a pixel signal corresponding to the incident light and generate image data, wherein the image sensing device operates to perform imaging operation in response to a control signal, a luminance acquisition unit to acquire the image data corresponding to first pixels among the plurality of pixels associated with a target region of an image of the scene captured by the image sensing device, a controllable item acquisition unit to acquire one or more sensitivity items indicative of sensitivity of each pixel to light, as a controllable item, and a set value calculation unit to generate the control signal to the imagine sensing device by calculating a set value for the controllable item based on the image data of the target region and the controllable item.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: March 26, 2024
    Assignee: SK HYNIX INC.
    Inventor: Kazuhiro Yahata