Abstract: The present technology relates to an electronic device. According to the present technology, a storage device having an improved operation speed may include a nonvolatile memory device, a main memory configured to temporarily store data related to controlling the nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device and the main memory under control of an external host. The main memory may aggregate and process a number of write transactions having continuous addresses, among write transactions received from the memory controller, equal to a burst length unit of the main memory.

Abstract: Disclosed is a semiconductor device for improving a gate induced drain leakage and a method for fabricating the same, and the method for fabricating semiconductor device may include forming a trench in a substrate; forming a gate dielectric layer over the trench, embedding a first dipole inducing portion in the gate dielectric layer on a lower side of the trench, filling a lower gate over the first dipole inducing portion, embedding a second dipole inducing portion in the gate dielectric layer on an upper side of the trench and forming an upper gate over the lower gate.

Abstract: There are provided a memory system and an operating method thereof. A memory system includes: a plurality of storage regions, each including a plurality of memory cells; and a controller configured to provide a plurality of read retry sets, determine an applying order of the plurality of read retry sets based on characteristics of a read error occurred in a first storage region among the plurality of storage regions, and apply at least one of the read retry sets, based on the applying order, for a read retry operation performed on the first storage region.

Abstract: The present invention provides a semiconductor device including a capping layer of a reduced thickness and capable of preventing regrowth of an interface layer caused by oxygen injection, and a method for fabricating the same. According to an embodiment of the present invention, the semiconductor device comprises: an interface layer on a substrate; a high-k layer on the interface layer; a gate electrode on the high-k layer; and a capping layer including a first oxygen barrier layer and a second oxygen barrier layer on the gate electrode.

Abstract: A method for fabricating a semiconductor device includes forming a trench in a substrate, forming a gate dielectric layer on a surface of the trench, forming a lower gate, which partially fills the trench, over the gate dielectric layer, forming a low work function layer over the lower gate, forming a spacer over the low work function layer, etching the low work function layer to be self-aligned with the spacer in order to form vertical gate on both upper edges of the lower gate, and forming an upper gate over the lower gate between inner sidewalls of the vertical gate.

Abstract: The present technology relates to an electronic device. According to the present technology, a computing system may include a storage device and a host. The storage device may include a plurality of zones. The host may receive storage area information including an optimal write size of an open zone among the plurality of zones from the storage device, determine a target size of data to be flushed to the storage device based on the optimal write size, a history size that is a size of data previously flushed to the storage device, and a buffer data of the host, and flush data having the target size among the buffer data to the storage device.

Abstract: A semiconductor module includes a semiconductor module body and a guide. The semiconductor module body extends in a first direction and a second direction intersecting the first direction. A plurality of connection terminals is arranged at one end of the semiconductor module in the second direction. A plurality of semiconductor devices is arranged on at least one side of the semiconductor module body. The guide is arranged at the other end of the semiconductor module body opposite to the one end to induce a flow of a cooling fluid toward the one end of the semiconductor module.

Abstract: A method for lane synchronization for an interconnection protocol, a controller, and a storage device. The method is suitable for a first device capable of linking to a second device according to the interconnection protocol, and includes providing data representing a de-skew interval which indicates a time interval between two consecutive periodic de-skew patterns. Then performing, by a hardware protocol engine for implementing a link layer of the interconnection protocol, a periodic de-skew pattern transmission adaptively over lanes from the first device to the second device according to the de-skew interval and in response to communication status information between the first device and the second device. The hardware protocol engine is configured to send a de-skew pattern periodically according to the de-skew interval when the communication status information satisfies a criterion, and to postpone sending of the de-skew pattern when the communication status information does not satisfy the criterion.

Abstract: Disclosed is an image sensor including a pixel array having a pixel pattern in which first to fourth 2×2 pixel groups are arranged in a clockwise direction, one infrared pixel is arranged in each of two 2×2 pixel groups that are not adjacent to each other, the same green pixels are arranged in a first diagonal direction, and red pixels and blue pixels are arranged in half in a second diagonal direction crossing the first diagonal direction, in a 4×4 unit pixel group.

Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers, which are stacked in an alternating manner; at least one support structure penetrating the stack structure in a substantially vertical manner, the at least one support structure being formed in a contact region; and a contact plug penetrating the stack structure in a substantially vertical manner, the contact plug being formed in the contact region, the contact plug being connected to a contact pad that is disposed on the bottom of the stack structure. The at least one support structure is formed of an oxide layer.

Abstract: Provided herein are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a lower substrate, a peripheral circuit component located on the lower substrate, a lower bonding layer including a lower capacitor structure, the capacitor structure located on the peripheral circuit component, an upper bonding layer including an upper capacitor structure, the upper bonding layer bonded to the lower bonding layer, a plurality of cells and a dummy insulating layer that are located on the upper bonding layer, and an upper substrate being located on the plurality of cells and the dummy insulating layer, wherein the upper capacitor structure is coupled to the lower capacitor structure.

Abstract: A clock generating circuit includes a buffer circuit and a phase compensating circuit. The buffer circuit buffers an input clock signal to generate an output clock signal. The phase compensating circuit detects a noise in a power voltage and adjusts, according to the noise of the power voltage, a voltage level of the input clock signal to compensate for a phase change of the output clock signal due to the noise of the power voltage.

Abstract: Methods for operating a motion recognition apparatus are disclosed. In some implementations, a method for recognizing a motion or gesture of an object may include operating an optical sensor device to capture light reflected from the object under illumination by light emitted toward the object, generating, by comparing the emitted light to the reflected light, a depth image including distance information indicating a distance between the optical sensor device and the object, generating, based on the light reflected from the object, an infrared image including infrared image information associated with the object, and determining the motion of the object based on at least one of the depth image and the infrared image.

Abstract: A capacitor includes: a plurality of bottom electrodes; a dielectric layer formed over the bottom electrodes; and a top electrode formed over the dielectric layer, wherein the top electrode includes a carbon-containing material and a germanium-containing material that fill a gap between the bottom electrodes.

Abstract: A memory device, and a method of operating the memory device, includes a memory block in which a plurality of cell pages are coupled to each of word lines. The memory device also includes a peripheral circuit configured to adjust a time point at which a verify voltage is applied to a selected word line among the word lines according to an order of performing a program operation during a verify operation of a selected cell page. The memory device further includes a control logic circuit configured to transmit, to the peripheral circuit, an operation code for adjusting a time point at which the verify voltage is output.

Abstract: An activation function processing method includes processing a first activation function in a first mode by referring to a shared lookup table that includes a plurality of function values of the first activation function; and processing a second activation function in a second mode by referring to the shared lookup table, the second activation function being a different function than the first activation function.

Abstract: An electronic device includes a semiconductor memory including material layers each including one or more low-resistance areas and one or more high-resistance areas, insulating layers stacked alternately with the material layers and including protrusions extending more than the material layers, conductive pillars passing through the insulating layers and the low-resistance areas, conductive layers located between the protrusions, and variable resistance layers interposed between the low-resistance areas and the conductive layers.

Abstract: A method for operating a memory includes: reading data and an error correction code from a memory core; correcting an error of the read data based on the read error correction code to produce error-corrected data; generating new data by replacing a portion of the error-corrected data with write data, the portion becoming a write data portion; generating a new error correction code based on the new data; and writing the write data portion of the new data and the new error correction code into the memory core.

Abstract: A fuse latch of a semiconductor device including PMOS transistors and NMOS transistors includes a data transmission circuit configured to transmit data to a first node and a second node in response to a first control signal, a latch circuit configured to latch the data received from the data transmission circuit through the first node and the second node, and a data output circuit configured to output the data latched by the latch circuit in response to a second control signal. NMOS transistors contained in the data transmission circuit, the latch circuit, and the data output circuit may be formed in first, fourth, and fifth active regions, PMOS transistors are formed in second and third active regions, and the first to fifth active regions are sequentially arranged in a first direction.

Abstract: The present technology relates to an electronic device. A memory controller that increases a hit ratio of a cache memory includes a memory buffer configured to store command data corresponding to a request received from a host, and a cache memory configured to cache the command data. The cache memory stores the command data by allocating cache lines based on a component that outputs the command data and a flag included in the command data.