Abstract: A digital broadcasting signal processing method for processing a multimedia stream by a set-top box is disclosed. A USB request command set is pre-defined in a digital signal receiving unit to support the set-top box. The digital signal receiving unit transmits data with the set-top box and controls the signal quality of the data transmission according to the USB request commands transmitted by the set-top box while the digital signal receiving unit connected with the set-top box via USB.

Abstract: An operation method of a memory includes the steps of calculating an offset of sequential write commands and the beginning of pages of a block of a non-volatile memory; shifting the block by the offset; and directly writing data from a host to the pages except the first and last pages of the block by the sequential write commands. In an embodiment, the pages are logical pages providing optimal writing efficiency and are determined before calculating the offset. The step of shifting the block by the offset is to increase corresponding logical block addresses (LBA) in the pages by the offset.

Abstract: A voltage regulator with adaptive Miller compensation includes a first amplifier and a second amplifier. An adaptive compensation circuit includes serially connected compensation capacitor and a compensation transistor coupled to the second amplifier. A bias circuit generates a proper bias control voltage to dynamically control the adaptive compensation circuit in a manner that the adaptive compensation transistor operates in a deep triode region with weakly-inverted channel or strongly-inverted channel. An output circuit generates an output voltage according to which the feedback voltage is generated. The resistance of the compensation transistor varies according to a load of the voltage regulator under control of the bias control voltage. The bias circuit generates a mirror current that copies at least a portion of a current flowing in the output circuit, and the bias control voltage is then generated according to the mirror current.

Abstract: A method of programming a multi-bit per cell non-volatile memory is disclosed. In one embodiment, the non-volatile memory is read to obtain a first data of a most-significant-bit (MSB) page on a current word line that succeeds in data reading, wherein the current word line follows a preceding word line on which data reading fails. At least one reference voltage is set. The MSB page on the current word line is secondly programmed with a second data according to the reference voltage, the second data being different from the first data.

Abstract: A voltage regulator with adaptive Miller compensation includes a first amplifier and a second amplifier. An adaptive compensation circuit includes serially connected compensation capacitor and a compensation transistor coupled to the second amplifier. A bias circuit generates a proper bias control voltage to dynamically control the adaptive compensation circuit in a manner that the adaptive compensation transistor operates in a deep triode region with weakly-inverted channel or strongly-inverted channel. An output circuit generates an output voltage according to which the feedback voltage is generated. The resistance of the compensation transistor varies according to a load of the voltage regulator under control of the bias control voltage. The bias circuit generates a mirror current that copies at least a portion of a current flowing in the output circuit, and the bias control voltage is then generated according to the mirror current.

Abstract: An exemplary embodiment of the present disclosure illustrates an automated mass production method, adapted for an automated mass production system in manufacturing at least an electronic device having a storage unit, the method includes steps of: determining a protocol type of the Auto Handler to select one of the agents; establishing a first communication protocol communication between the MP tool module and the selected agent; establishing a second communication protocol communication between the selected agent and the Auto Handler; the Auto Handler outputting a processing command to the selected agent; the selected agent converting the processing command into a MP tool module executable MP tool instruction; and the selected agent outputting the corresponding MP tool instruction to the MP tool module so as to have the MP tool module executed the MP tool instruction to automatically perform a corresponding mass production process to the electronic device.

Abstract: A method of twice programming a multi-bit per cell non-volatile memory with a sequence is disclosed. At least one page at a given word line is firstly programmed with program data by a controller of the non-volatile memory, and at least one page at a word line preceding the given word line is secondly programmed with the same program data by the controller.

Abstract: A memory controller includes a mixed buffer and an arbiter. The mixed buffer includes at least one single-port buffer and at least one multi-port buffer for managing data flow between a host and a storage device. The arbiter determines an order of access to the mixed buffer among a plurality of masters. The data to be written or read are partitioned into at least two parts, which are then moved to the single-port buffer and the multi-port buffer, respectively.

Abstract: A method of dynamic data storage for error correction in a memory device is disclosed. Data for storage is received, the received data is encoded and error correction code (ECC) is generated. The encoded data is stored in the memory device that includes a plurality of pages each having a plurality of data partitions. More corrected errors a marked page has, a smaller portion with a space of at least one datum of each of the corresponding data partitions associated with the marked page is allocated to store the encoded data, while a size of the ECC is fixed, thereby increasing capability of correcting errors in the marked page.

Abstract: A linear voltage regulating circuit adaptable to a logic system is disclosed. A first linear voltage regulator receives an input voltage and a first reference voltage. A second linear voltage regulator has a load driving capability lower than the first linear voltage regulator, and the second linear voltage regulator receives the input voltage and a second reference voltage. An output node of the first linear voltage regulator and an output node of the second linear voltage regulator are directly connected at a single common output node. A single common capacitor is connected between the common output node and a ground.

Abstract: A method of programming a multi-bit per cell non-volatile memory is disclosed. In one embodiment, the non-volatile memory is read to obtain a first data of a most-significant-bit (MSB) page on a current word line that succeeds in data reading, wherein the current word line follows a preceding word line on which data reading fails. At least one reference voltage is set. The MSB page on the current word line is secondly programmed with a second data according to the reference voltage, the second data being different from the first data.

Abstract: The present invention is directed to a bit-level memory controller and method adaptable to managing defect bits of a non-volatile memory. A bad column management (BCM) unit retrieves a bit-level mapping table, in which defect bits are respectively marked, based on which the BCM unit constructs a bit-level script (BLS) that contains a plurality of entries denoting defect-bit groups respectively. An internal buffer is configured to store data managed by the BCM unit according to the BLS.

Abstract: A method of dynamic data storage for error correction in a memory device is disclosed. Data for storage is received, and the received data is then encoded and associated error correction code (ECC) is generated. The encoded data is stored in a portion of a data partition of the memory device, wherein percentage of the stored data in the data partition is determined according to an amount of corrected errors associated with the data partition or is predetermined.

Abstract: The present invention is directed to a clock generator and a method of generating a clock signal. A digital control oscillator (DCO) generates a clock signal. A first frequency calibration unit extracts a periodic signal and determines a frequency error quantity between the extracted periodic signal and a derived clock signal. A second frequency calibration unit generates a coarse tuning signal when an absolute value of the frequency error quantity is greater than a first predetermined threshold, and generates a fine tuning signal when the absolute value of the frequency error quantity is less than a second predetermined threshold.

Abstract: A method of sorting a multi-bit per cell non-volatile memory includes programming and reading to test an n-bit-per-cell (n-bpc) non-volatile memory, which has a plurality of m-bpc pages, where m is a positive integer from 1 through n. If the m-bpc page fails the test, counting a block associated with the failed m-bpc page to (m-1)-bpc blocks, wherein each said m-bpc page is subjected to at most one time of programming and reading. When m is equal to 1, the 0-bpc block corresponds to a bad block.

Abstract: A program method for a non-volatile memory is disclosed. At least two blocks in the non-volatile memory are configured as 1-bit per cell (1-bpc) blocks. The data of the configured blocks are read and written to a target block in such a way that the data of each said configured block are moved to pages of a same significant bit. In another embodiment, the data of the configured blocks excluding one block are read and written to the excluded block.

Abstract: A method and system for adaptively finding reference voltages for reading data from a multi-level cell (MLC) flash memory is disclosed. According to one embodiment, a first total number of cells of the flash memory above a first threshold voltage in a shifted threshold voltage distribution is provided. Search to find a second threshold voltage such that a second total number of the cells above the second threshold voltage is approximate to the first total number. An initial reference voltage or voltages of the initial threshold voltage distribution are shifted with an amount approximate to a voltage difference between the second threshold voltage and the first threshold voltage, thereby resulting in a new reference voltage or voltages for reading the data from the MLC flash memory.

Abstract: A method and apparatus of generating the soft value for a memory device is disclosed. Memory read-related parameters are set, and data are read out of the memory device according to the set parameters. The data reading is performed for pre-determined plural iterations, thereby obtaining the soft value according to the read-out data and the set parameters.

Abstract: A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged.

Abstract: A method of programming a multi-bit per cell non-volatile memory is disclosed. In one embodiment, the non-volatile memory is read to obtain a first data of a most-significant-bit (MSB) page on a current word line that succeeds in data reading, wherein the current word line follows a preceding word line on which data reading fails. At least one reference voltage is set. The MSB page on the current word line is secondly programmed with a second data according to the reference voltage, the second data being different from the first data.