Abstract: A uniform coding system for a flash memory is disclosed. A statistic decision unit determines a coding word according to a plurality of inputs. An inverse unit controllably inverts input data to be encoded. The input data are then encoded into encoded data according to a statistic determined by the statistic decision unit.

Abstract: A flash memory system includes a path selector to determine to write to a non-volatile memory, a volatile memory or both the non-volatile memory and the volatile memory when the flash memory system is to write data. A record is stored in the non-volatile memory which is updated the status of the non-volatile memory after each one or more writing operations. When the flash memory system is powered on after a power loss, it could be recovered to a command executed prior to the power loss or to any checkpoint prior to the power loss by using the record.

Abstract: A method and system for obtaining a reference block on which reference voltages may be found for a MLC flash memory are disclosed. A first block and a second block are provided in the flash memory. A memory controller alternatively controls one of the first and the second blocks to act as the reference block and the other one as a cycle block in a respective period, during which the reference block stays idle and the cycle block is subjected to program/erase cycles.

Abstract: A method of dynamic data storage for error correction in a memory device is disclosed. Data for storage is received, and the received data is then encoded and associated error correction code (ECC) is generated. The encoded data is stored in a portion of a data partition of the memory device, wherein percentage of the stored data in the data partition is determined according to an amount of corrected errors associated with the data partition or is predetermined.

Abstract: A method of reducing coupling effect in a flash memory is disclosed. A neighboring page is read, and a flag is set active if the neighboring page is an interfering page. Data are read from the neighboring page at least two more times using at least two distinct read voltages respectively. The threshold-voltage distributions associated with an original page and the neighboring page are transferred according to the read data and the flag.

Abstract: A method and system for adaptively finding reference voltages for reading data from a multi-level cell (MLC) flash memory is disclosed. According to one embodiment, a first total number of cells of the flash memory above a first threshold voltage in a shifted threshold voltage distribution is provided. Search to find a second threshold voltage such that a second total number of the cells above the second threshold voltage is approximate to the first total number. An initial reference voltage or voltages of the initial threshold voltage distribution are shifted with an amount approximate to a voltage difference between the second threshold voltage and the first threshold voltage, thereby resulting in a new reference voltage or voltages for reading the data from the MLC flash memory.

Abstract: An error correction method for a memory device is disclosed. A base reading of a memory device is performed, and an error correction code (ECC) decoding is performed on the data read out of the memory device. The memory device is further read when the result of the ECC decoding is not strongly determined, wherein extra information acquired in the further reading of the memory device is used in the ECC decoding.

Abstract: A method and system for obtaining a reference block on which reference voltages may be found for a MLC flash memory are disclosed. A first block and a second block are provided in the flash memory. A memory controller alternatively controls one of the first and the second blocks to act as the reference block and the other one as a cycle block in a respective period, during which the reference block stays idle and the cycle block is subjected to program/erase cycles.

Abstract: A method and system for adaptively finding reference voltages for reading data from a multi-level cell (MLC) flash memory is disclosed. According to one embodiment, information about an initial threshold voltage distribution is firstly provided. A first threshold voltage in the initial threshold voltage distribution is then associated with a second threshold voltage in a shifted threshold voltage distribution to be determined, such that the information corresponding to the first threshold voltage is approximate to the information corresponding to the second threshold voltage. Accordingly, initial reference voltage or voltages of the initial threshold voltage distribution are shifted with an amount approximate to difference between the first threshold voltage and the second threshold voltage, thereby resulting in new reference voltage or voltages for reading the data from the MLC flash memory.

Abstract: The block groups of a multiple data channel flash memory storage device are detected for defective blocks. The block group containing any defective blocks is divided into subgroups, each of which contains only defective blocks or only good blocks. The subgroups containing only good blocks are selected to establish a new block group having the same amount of blocks as that of the original block groups.

Abstract: A method and related system for programming connections between a NAND flash memory controller and a plurality of NAND flash memory modules includes the NAND flash memory controller generating a switch signal and a swap signal according to a condition of one of the plurality of NAND flash memory modules, a remap module selectively coupling the plurality of NAND flash memory modules to the NAND flash memory controller according to the switch signal, and a swap module selectively coupling the plurality of NAND flash memory modules to the NAND flash memory controller according to the swap signal.

Abstract: An operation method for a non-volatile memory structure formed between two doping regions serving as bit lines in a semiconductor substrate, the non-volatile memory structure comprising a first conductive line serving as a select gate and being formed above the semiconductor substrate, two conductive blocks serving as floating gates and being formed at the two sides of the first conductive line and insulated from the first conductive line with two first dielectric spacers therebetween, a first dielectric layer formed on the two second conductive blocks, a second conductive line serving as a word line and being formed on the first dielectric layer and substantially perpendicular to the two doping regions.

Abstract: A method for managing defect blocks in a non-volatile memory essentially comprises the steps of detecting defect blocks in the non-volatile memory, storing addresses of the defect blocks in a table block of the non-volatile memory, and setting the non-volatile memory to be read-only if the quantity of defect blocks in the non-volatile memory exceeds a threshold and no free blocks remain in the non-volatile memory. In a preferred embodiment, the free pages in the defect block continue to be programmed before setting the non-volatile memory to be read-only.

Abstract: A method of memory management for an apparatus having a non-volatile memory and a volatile memory includes the steps of forming a tree structure of entries in the volatile memory, in which the tree structure has a left branch and a right branch, and a difference of heights of the left branch and the right branch is equal to or less than one; and accessing an entry in the volatile memory through the tree structure.

Abstract: An operation method of a memory includes the steps of calculating an offset of sequential write commands and the beginning of pages of a block of a non-volatile memory; shifting the block by the offset; and directly writing data from a host to the pages except the first and last pages of the block by the sequential write commands. In an embodiment, the pages are logical pages providing optimal writing efficiency and are determined before calculating the offset. The step of shifting the block by the offset is to increase corresponding logical block addresses (LBA) in the pages by the offset.

Abstract: A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged.

Abstract: A method is employed to manage a memory, e.g., a flash memory, including a plurality of paired pages. Each paired page includes a page and a respective risk zone. For each write command, at least one unwritten page is selected for writing new data. For each unwritten page whose risk zone includes at least one written page, each written page is copied or backed up, and the new data is written to the unwritten page. For each unwritten page whose risk zone lacks a written page, the new data is written to the unwritten page. In an embodiment, the written page is copied only if the unwritten page and the written page are operated by different write commands.

Abstract: A method of wear leveling for a non-volatile memory is performed as follows. First, the non-volatile memory is divided into a plurality of zones including at least a first zone and a second zone. The first zone is written and/or erased in which one or more logical blocks have higher writing hit rate, and therefore the corresponding physical blocks in the first zone will be written more often. The next step is to find one or more free physical blocks in second zone. The physical blocks of the first zone are replaced by the physical blocks of the second zone if the number of write and/or erase to the first zone exceeds a threshold number. The replacement of physical blocks in the first zone by the physical blocks in the second zone may include the steps of copying data from the physical blocks in the first zone to the physical block in the second zone, and changing the pointer of logical blocks to point to the physical blocks in the second zone.

Abstract: According to the method of wear leveling for a non-volatile memory of the present invention, the non-volatile memory is divided into a plurality of windows, and a mapping table is built in which the logical block addresses having frequently accessed data are allocated equally to the plurality of windows. The logical block addresses may store a File Allocation Table (FAT) or a directory table; therefore the windows they locate will be written or erased more frequently. In an embodiment, the logical block addresses having frequently accessed data are allocated on a one-to-one basis to the plurality of windows. For example, the plurality of windows may comprise Windows 0, 1, 2 and 3, the logical block addresses comprise logical block addresses 0, 1, 2 and 3, and logical block addresses 0, 1, 2 and 3 point to Windows 0, 1, 2 and 3, respectively.

Abstract: A method for managing defect blocks in a non-volatile memory essentially comprises the steps of detecting defect blocks in the non-volatile memory, storing addresses of the defect blocks in a table block of the non-volatile memory, and setting the non-volatile memory to be read-only if the quantity of defect blocks in the non-volatile memory exceeds a threshold and no free blocks remain in the non-volatile memory. In a preferred embodiment, the free pages in the defect block continue to be programmed before setting the non-volatile memory to be read-only.