Abstract: Apparatus and methods for modulation partition and transmission via multiple antennas for enhanced transmit power capability are provided herein. In certain embodiments, an RF communication system includes a transceiver that generates a first RF signal and a second RF signal corresponding to partitions of a modulated RF signal. For example, the first RF signal and the second RF signal can be associated with different RB allocations of one or more channels of a frequency band. The RF communication system further includes a first transmit chain that processes the first RF signal to generate a first RF output signal for transmission on a first antenna, and a second transmit chain that processes the second RF signal to generate a second RF output signal for transmission on a second antenna.

Abstract: Apparatus and methods for distributing millimeter wave cellular service over a face of a building are disclosed. In certain embodiments, an antenna assembly includes an antenna upper unit configured to extend from a top of a building, such as from a roof. The antenna upper unit includes a first linear antenna array that radiates a transmit beam having a disc-shaped pattern. The antenna assembly includes an antenna lower unit configured to extend from the building beneath the antenna upper unit. The antenna lower unit includes a second linear antenna array that receives the transmit beam.

Abstract: In one aspect, an apparatus includes: a fast Fourier transform (FFT) engine to receive and convert a plurality of orthogonal frequency division multiplexing (OFDM) samples into a plurality of frequency carriers; a detector coupled to the FFT engine to determine a channel estimate for a first frequency carrier using a first channel estimate for the first frequency carrier and a plurality of other channel estimates, each of the plurality of other channel estimates for one of a plurality of neighboring frequency carriers within an evaluation window, and determine a log likelihood ratio (LLR) for the first frequency carrier using the channel estimate for the first frequency carrier; and a decoder coupled to the detector to decode a first OFDM symbol comprising the first frequency carrier using the LLR for the first frequency carrier.

Abstract: A system includes a plurality of line cards and a timing card. A clock generation circuit on the timing card generates a clock signal which is pulse width modulated according to information to be transmitted. A clock line supplies the pulse width modulated clock signal to the line cards. The timing card sends a first control word to the plurality of line cards over the clock line after sending a beacon. The first control word includes a size field specifying a first length of first data following the first control word. The timing card sends time of day information over the clock line to the line cards following the first control word. The time of day information may be encrypted. A second control word follows the time of day information. One or more additional control words can follow the second control word before the next beacon.

Abstract: Apparatus and methods for load modulated power amplifiers are provided. In certain embodiments, a load modulated power amplifier system includes a power amplifier that receives a radio frequency signal at an input and provides an amplified radio frequency signal at an output, and a controllable load impedance coupled to the output of the power amplifier. The controllable load impedance receives an envelope signal that changes in relation to an envelope of the radio frequency signal, and the envelope signal is operable to control an impedance of the controllable load impedance to modulate a load at the output of the power amplifier.

Abstract: An impedance tuning circuit includes a first node and a second node, and an inductance circuit including an inductor and a first switch connected in series such that the inductor is connected to the first node and the first switch is connected to the second node. The inductance circuit further includes a second switch implemented between ground and a third node between the inductor and the first switch, such that the inductance circuit is capable of providing a series inductance path between the first and second nodes or a shunt inductance path between the third node and the ground.

Abstract: Radio-frequency (RF) switching devices having improved voltage handling capability. In some embodiments, a switching device can include a first terminal and a second terminal, and a plurality of switching elements connected in series to form a stack between the first terminal and the second terminal. The switching elements can have a non-uniform distribution of a parameter that results in the stack having a first voltage handling capacity that is greater than a second voltage handling capacity corresponding to a similar stack having a substantially uniform distribution of the parameter.

Abstract: Surface acoustic wave resonators are disclosed. In certain embodiments, a surface acoustic wave resonator can include a high impedance layer, a piezoelectric layer over the high impedance layer, an interdigital transducer electrode over the piezoelectric layer, and a low impedance layer between the high impedance layer and the piezoelectric layer. An acoustic impedance of the high impedance layer is greater than an acoustic impedance of the piezoelectric layer. An acoustic impedance of the low impedance layer is lower than the acoustic impedance of the high impedance layer. The piezoelectric layer can have a cut angle in a range from 115° to 135°. The surface acoustic wave resonator is configured to generate a Rayleigh mode surface acoustic wave having a wavelength of ?.

Abstract: A line card receives a SYNC input signal and a first system clock signal. The line card generates a second system clock signal in a PLL and generates a SYNC output signal by dividing the second system clock signal in a divider circuit. The SYNC output signal is fed back as a SYNC feedback signal. The line card determines determining a closest edge of the first system clock signal to a transition of the SYNC input signal and determines a time difference between the closest edge of the first system clock signal and a transition of the SYNC feedback. The SYNC output signal is adjusted based on the time difference using a coarse adjustment by adjusting a divide ratio of the divider circuit and using a fine adjustment in the PLL based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.

Abstract: Architectures and techniques relate to ganged and switch combined systems for satellite-navigation-band filters. For example, a system can include a mid-range-band filter, a satellite-navigation-band filter, and circuitry configured to receive a signal from an antenna and route the signal to the mid-range-band filter and the satellite-navigation-band filter. The circuitry can be implemented in at least one of (i) a ganged configuration in which the mid-range-band filter and the satellite-navigation-band filter receive the signal through a common input node or (ii) a switch-combined configuration in which two or more switch arms are configured to be controlled simultaneously to route the signal to the mid-range-band filter and the satellite-navigation-band filter.

Abstract: A switching component and switch assembly. The switching component comprises a first control node, a common node, a plurality of intermediate nodes, a second control node, and a capacitive node; a plurality of transistors connected in series between the control node and the common node, one of the plurality of intermediate nodes being defined between each series connected pair of transistors, each transistor of the plurality of transistors having a gate coupled to the second control node; and a plurality of capacitive components, one capacitive component being coupled between each intermediate node and the capacitive node, a voltage at the capacitive node being configured to be varied with a voltage at the second control node such that, at each intermediate node, the capacitive component is configured to accrue an opposite charge to the transistors.

Abstract: Aspects of this disclosure relate to a tunable filter with tunable rejection. The tunable filter includes mutually coupled inductors and a tunable impedance circuit electrically connected to at least one of the mutually coupled inductors. The tunable impedance circuit is configured to adjust at least two notches in a frequency response of the tunable filter by changing a state of a switch. The tunable filter can filter a radio frequency signal. Related methods, radio frequency systems, radio frequency modules, and wireless communication devices are also disclosed.

Abstract: Baluns with integrated matching networks are provided herein. In certain embodiments, a balun structure includes a first pair of coupled lines, a second pair of coupled lines and a transmission line. Additionally, a first port of the balun is connected to a reference voltage by way of a first line of the first pair of coupled lines, the transmission line, and a first line of the second pair of coupled lines. Furthermore, a second port of the balun is connected to the reference voltage by way of a second line of the first pair of coupled lines, while a third port of the balun is connected to the reference voltage by way of a second line of the second pair of coupled lines. The first port serves as an unbalanced signal terminal, while the second port and the third port serve as positive and negative signal terminals.

Abstract: A power management device is disclosed, including a first DC-DC converter coupled to a first output voltage line, a second DC-DC converter coupled to a second output voltage line, a first set of switches associated with the first DC-DC converter, and a second set of switches associated with the second DC-DC converter. The power management device may further include a controller configured to toggle one or more switches of the first set of switches and one or more switches of the second set of switches, and a multi-mode radio-frequency front-end block communicatively coupled to the controller.

Abstract: A line card of a network box receives a SYNC input signal and generates a first time stamp based on receipt of the SYNC input signal. The line card generates a system clock signal in a phase-locked loop and generates a SYNC output signal by dividing the system clock signal in a divider circuit. The SYNC output signal is fed back to an input terminal as a SYNC feedback signal. A time stamp is generated based on receipt of the SYNC feedback signal. The line card determines a time between the SYNC input signal and the SYNC feedback signal based on the first time stamp and the second time stamp. The timing of the SYNC output signal is adjusted based on the time difference using a coarse time adjustment by adjusting a divide ratio of the divider circuit and using a fine time adjustment in the phase-locked loop based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.

Abstract: A surface mount device inductor has a package casing sized to attenuate electromagnetic coupling between the inductor coils of the surface mount device inductors. The surface mount device inductor includes an inductor coil, an anode structure disposed over a first end of the inductor coil and a cathode structure disposed over a second end of the inductor coil opposite the first end, the cathode structure being spaced apart from the anode structure. One or both of the anode structure and the cathode structure comprise a shield portion disposed at least partially over the inductor coil to thereby reduce electromagnetic coupling between adjacent surface mount device inductors. The package casing makes the surface mount device inductors self-shielding. The surface mount device inductors can be incorporated into a radiofrequency module, and can be incorporated into a front end system of a wireless mobile device.

Abstract: A transistor can include a plurality of source regions and a plurality of drain regions arranged in an alternating manner, with each of the source regions and the drain regions being implemented as a first type active region, and a plurality of gate structures implemented relative to the source regions and the drain regions such that application of a voltage to each gate structure results in formation of a conductive channel between a respective pair of source and drain regions. The transistor can further include a body region configured to provide the respective conductive channel upon the application of the voltage to the corresponding gate structure, with the body region being implemented as a second type active region. The transistor can further include a recessed region defined by an end of each drain region and one or both of the gate structures adjacent to the drain region.

Abstract: An automated method of cleaning trays used in handling circuit device packages includes the steps of: placing a plurality of trays on a tray loading station of an automated tray cleaning machine; lowering in an automated manner a first tray of the plurality of trays onto a conveyor; conveying in an automated manner the first tray from the tray loading station into a cleaning chamber; automatically applying pressurized air in the cleaning chamber to one or more surfaces of the first tray to remove debris from the first tray; conveying in an automated manner the first tray out of the cleaning chamber and to a tray unloading station; and raising in an automated manner the first tray above the conveyor.

Abstract: In some embodiments, a power amplification system can comprise a current source, an input switch configured to alternatively feed current from the current source to a high-power circuit path and a low-power circuit path, and a band switch including a switch arm for switching between a plurality of bands. Each of the high-power circuit path and the low-power circuit path can be connected to the switch arm.

Abstract: A method of adjusting an impedance of a power amplifier of a radio frequency system for matching with an antenna switch die is disclosed. In one aspect, the method includes connecting the power amplifier to the antenna switch die via an impedance adjustment circuit, the impedance adjustment circuit including an input node, an output node, a plurality of electrical components arranged between the input node and the output node, and at least one switch configured to selectively electrically connect at least one of the electrical components to the input node and the output node. The method further includes determining an Error Vector Magnitude of the radio frequency system for each of a plurality of states of the at least one switch, and controlling the at least one switch to enter the state of the plurality of states that minimizes the Error Vector Magnitude of the radio frequency system.