Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

Abstract: A method for minimizing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer, wherein a curve representing the distortion as a function of a power of the input or output signal exhibits a trough around a given power (PDip), the method comprises applying, between the radiofrequency circuit and the semiconductor substrate, an electrical potential difference (VGB) chosen so as to move the trough toward a given operating power of the radiofrequency circuit.

Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer.

Abstract: A method for determining a suitable implanting energy of at least two atomic species in a donor substrate to create a weakened zone defining a monocrystalline semiconductor layer to be transferred onto a receiver substrate, comprises the following steps: (i) forming a dielectric layer on at least one of the donor substrate and the receiver substrate; (ii) co-implanting the species in the donor substrate; (iii) bonding the donor substrate on the receiver substrate; (iv) detaching the donor substrate along the weakened zone to transfer the monocrystalline semiconductor layer and recover the remainder of the donor substrate; (v) inspecting the peripheral crown of the remainder of the donor substrate, or of the receiver substrate on which the monocrystalline semiconductor layer was transferred at step (iv); (vi) if the crown exhibits zones transferred onto the receiver substrate, determining the fact that the implanting energy at step (ii) is too high; (vii) if said the crown does not exhibit zones transferred on

Abstract: A method for producing a layer of composition AA?BO3, where A is composed of at least one element selected from: Li, Na, K, Ca, Mg, Ba, Sr, Pb, La, Bi, Y, Dy, Gd, Tb, Ce, Pr, Nd, Sm, Eu, Ho, Zr, Sc, Ag and Tl, and B is composed of at least one element selected from: Nb, Ta, Sb, Ti, Zr, Sn, Ru, Fe, V, Sc, C, Ga, Al, Si, Mn Zr and Tl, wherein the method comprises the steps of: providing a donor substrate of composition ABO3, forming a layer of composition ABO3 by thinning the donor substrate, and, before and/or after the thinning step, exposing the ABO3 layer to a medium containing ions of an element A? belonging to the same list of elements as A, A? being different from A, such that the ions penetrate into the layer to form a layer of composition AA?BO3.

Abstract: Methods of forming semiconductor structures comprising one or more cavities, which may be used in the formation of microelectromechanical system (MEMS) transducers, involve forming one or more cavities in a first substrate, providing a sacrificial material within the one or more cavities, bonding a second substrate over a surface of the first substrate, forming one or more apertures through a portion of the first substrate to the sacrificial material, and removing the sacrificial material from within the one or more cavities. Structures and devices are fabricated using such methods.

Abstract: A method for fabricating a strained semiconductor-on-insulator substrate includes bonding a donor substrate to a receiving substrate, with a dielectric layer at the interface, and transferring a monocrystalline semiconductor layer from the donor substrate to the receiving substrate. A portion is cut from a stack formed from the transferred monocrystalline semiconductor layer from the dielectric layer and from the strained semiconductor material layer. The cutting results in the relaxation of the strain in the strained semiconductor material, and in the application of at least a part of the strain to the transferred monocrystalline semiconductor layer. The method also involves the formation, on the strained semiconductor material layer of the receiving substrate, of a dielectric bonding layer or of a bonding layer consisting of the same relaxed, or at least partially relaxed, monocrystalline material as the monocrystalline semiconductor layer of the donor substrate.

Abstract: A method of providing a layer of solid electrolyte comprises providing a host substrate including a crystalline solid electrolyte layer, and transferring the crystalline solid electrolyte layer from the host substrate to a receiver substrate. The method may be used to manufacture various devices, such as solid oxide fuel cells, oxygen sensors, batteries, and donor structures.

Abstract: A method for measuring thickness variations in a first layer of a semiconductor structure includes: acquiring an image of at least one zone of the surface of the structure, processing the acquired image so as to determine a map of the thickness variations of the first layer, and comparing the intensity of each pixel of the image with a predetermined calibration curve, the calibration curve being determined for a given thickness of a second layer of the structure, and measuring the thickness of the second layer in the at least one zone, -if the measured thickness is different from the thickness of the second layer considered in the calibration curve, using a correction curve to determine a corrected map of thickness variations of the first layer.

Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.

Abstract: A manufacturing method including supplying a first substrate including a first face designated front face, the front face being made of a III-V type semiconductor, supplying a second substrate, forming a radical oxide layer on the front face of the first substrate by executing a radical oxidation, assembling, by a step of direct bonding, the first substrate and the second substrate so as to form an assembly including the radical oxide layer intercalated between the first and second substrates, executing a heat treatment intended to reinforce the assembly interface, and making disappear, at least partially, the radical oxide layer.

Abstract: A method for preparing a crystalline semiconductor layer in order for the layer to be provided with a specific lattice parameter involves a relaxation procedure that is applied for a first time to a first start donor substrate in order to obtain a second donor substrate. Using the second donor substrate as the start donor substrate, the relaxation procedure is repeated for a number of times that is sufficient for the lattice parameter of the relaxed layer to be provided with the specific lattice parameter. A set of substrates may be obtained by the method.

Abstract: A method for determining the size of a void-type defect in a top side of a structure comprising a top layer placed on a substrate, the defect being located in the top layer, includes introducing the structure into a reflected darkfield microscopy device in order to generate, from a light ray scattered by the top side, a defect-related first signal and a roughness-related second signal. The intensity of the roughness-related second signal is captured with a plurality of pixels. The intensity captured by each pixel is compared with the intensities captured by neighboring pixels. It is defined whether or not the pixel is contained in an abnormal zone. The standard deviation of the intensity values captured by the pixels of the abnormal zone is extracted, and the size of the void-type defect associated with the abnormal zone is determined from the extracted standard deviation. A new device may be used for carrying out such a method.

Abstract: A method of fabrication of a semiconductor element includes a step of rapid heat treatment in which a substrate comprising a base having a resistivity greater than 1000 Ohm·cm is exposed to a peak temperature sufficient to deteriorate the resistivity of the base. The step of rapid heat treatment is followed by a curing heat treatment in which the substrate is exposed to a curing temperature between 800° C. and 1250° C. and then cooled at a cooldown rate less than 5° C./second when the curing temperature is between 1250° C. and 1150° C., less than 20° C./second when the curing temperature is between 1150° C. and 1100° C., and less than 50° C./second when the curing temperature is between 1100° C. and 800° C.

Abstract: A thermal treatment system includes a chamber capable of receiving a plurality of substrates, a gas intake path in a distal portion of the chamber located opposite an area for entry of substrates into the chamber, and an outlet path for the gas and/or volatile species generated during the thermal treatment. The outlet path is located in a proximal portion of the chamber located near the area for entry of the substrates into the chamber. The system further includes a collector device in the proximal portion of the chamber. The collector device has a confinement opening oriented toward the distal portion of the chamber, and the collector device defines a compartment communicating with the outlet path, the compartment being configured so that the gas and the volatile species enter into the compartment via the confinement opening and pass through the compartment to reach the outlet path.

Abstract: A semiconductor device, in particular a solar cell is formed on the basis of a hybrid deposition strategy using MOCVD and MBE in order to provide lattice matched semiconductor compounds. To this end, the MBE may be applied for providing a nitrogen-containing semiconductor compound that allows a desired low band gap energy and a lattice matched configuration with respect to gallium arsenide substrates.

Abstract: A method of transferring blocks of semiconductor material to a substrate comprises the following steps: a. providing an intermediate substrate, the intermediate substrate comprising, on one of its faces, blocks, the blocks comprise a monocrystalline material, the blocks comprising an embrittlement area delimiting a block portion intended to be transferred onto a final substrate; b. executing an assembling step by putting a free surface of each of the blocks in contact with the final substrate; and c. executing, after the assembling step, detachment at the embrittlement area of each of the blocks. During the assembling step, the intermediate substrate deforms so that the free surfaces of the blocks become coplanar.

Abstract: The disclosure relates to a device for measuring an electrical characteristic of a substrate comprising a support made of a dielectric material having a bearing surface, the support comprising an electrical test structure having a contact surface flush with the bearing surface of the support, the bearing surface of the support and the contact surface of the electrical test structure being suitable for coming into close contact with a substrate. The measurement device also comprises at least one connection bump contact formed on another surface of the support and electrically linked to the electrical test structure. This disclosure also relates to a system for characterizing a substrate and a method for measuring a characteristic of a substrate employing the measurement device.

Abstract: This disclosure relates to a solar cell assembly structure for supporting a concentrator photovoltaic cell comprising a semiconducting structure and a diode, wherein the semiconducting structure comprises a first semiconducting region at least a part of which for placing the concentrator photovoltaic cell structure, and a second semiconducting region for realizing the diode within or on the second semiconducting region and wherein the part of the first semiconducting region for placing the concentrator photovoltaic cell structure and the second semiconducting region are not vertically overlapping.

Abstract: A useful layer is layered onto a support by a method that includes the steps of forming an embrittlement plane by implanting light elements into a first substrate, so as to form a useful layer between such plane and one surface of the first substrate; applying the support onto the surface of the first substrate so as to form an assembly to be fractured; applying a heat treatment for embrittling the assembly to be fractured; and initiating and propagating a fracture wave into the first substrate along the embrittlement plane. The fracture wave is initiated in a central area of the embrittlement plane and the propagation speed of the wave is controlled so that the velocity thereof is sufficient to cause the interactions of the fracture wave with acoustic vibrations emitted upon the initiation and/or propagation thereof, if any, are confined to a peripheral area of the useful layer.