Abstract: A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCI). The programming method of the present invention enables multi-bit programming of the PMOS MTP flash memory cells, thereby increasing the programming speed while preserving low power consumption.

Abstract: A gas inlet configured to convey a gas stream from a feed source to the system. A hydrogen sulfide removal stage includes a first vessel configured to receive a first media. A primary compression stage is configured to elevate a pressure of the gas stream. A moisture removal stage is configured to condense and separate remaining moisture from the gas stream. A siloxane removal stage includes a second vessel configured to receive a second media. A carbon dioxide removal stage includes a single-stage membrane configured to separate carbon dioxide from the gas stream by a permeability characteristic of the gas stream. A secondary compression stage is configured to elevate a pressure of the gas stream to a level suitable for distribution to CNG-compatible vehicles. An electrical generator set has a prime mover configured to be fueled by the gas stream.

Abstract: Exhaust after-treatment systems and methods are disclosed. An example system includes a selective catalytic reduction on filter (SCRF) and a selective catalytic reduction (SCR) catalyst positioned downstream of the SCRF. The system also includes a first reductant doser positioned upstream of the SCRF and a second reductant doser positioned downstream of the SCRF and upstream of the SCR catalyst. The system further includes first and second nitrogen oxide (NOx) sensors positioned upstream of the first reductant doser, a third NOx sensor positioned downstream of the SCRF and upstream of the second reductant doser, and a catalyst positioned upstream of the first reductant doser.

Abstract: A topical formulation comprising a first active agent that is pharmaceutically acceptable salt of a cationic bisbiguanide such as chlorhexidine digluconate (CHG), a secnd active agent which is a cationic quaternary ammonium compound such as cetylpyridinium chloride (CPC), methylisothiazolone, or chloroxylenol, and a propellant; and an aerosol dispenser containing the topical formulation. The topical formulation can be sprayed onto exposed skin to prevent or reduce the risk of skin infection.

Abstract: Provided herein are switching methods and systems for switching a patch cord fiber in a fiber management system having non-tensioned patch cord fibers, from a first adapter to a second adapter. Switching comprises disconnecting the patch cord fiber connector from the first adapter; distinguishing the disconnected patch cord fiber, at a region removed from the connector, from other patch cord fibers according to a position of the patch cord fiber in the fiber management system; pulling the distinguished patch cord fiber at the handling region to receive and clasp the disconnected connector, wherein the pulling is carried out to disentangle the pulled patch cord fiber from the other patch cord fibers; and connecting the clasped connector to the second adapter. The patch cord fibers are thus manages at edges thereof only, with no slack control required.

Abstract: A display system for providing user interactive, immersive activity is disclosed. The system includes a simulation controller and a video display system having an actively viewable height of at least six feet or more, the video display system having one or more actively viewable surfaces. One or more input devices are configured to receive inputs from a user. The simulation controller is configured to cause to be displayed display on the one or more actively viewable surfaces a user interactive, immersive activity in a first mode. The simulation controller is responsive to receiving a first input from the one or more input devices to activate a second mode in which content unrelated to the user interactive, immersive activity is caused to be displayed on the one or more actively viewable surfaces.

Abstract: A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCI). The programming method of the present invention enables multi-bit programming of the PMOS MTP flash memory cells, thereby increasing the programming speed while preserving low power consumption.

Abstract: Feedback and impedance circuits, devices and methods for broadband radio-frequency (RF) amplifiers. An RF amplifier architecture can include an amplifier having a first field-effect transistor (FET) and a second FET arranged in a cascode configuration. The gate of the first FET can be configured to receive an RF signal, the drain of the first FET can be coupled to the source of the second FET, and the drain of the second FET can be configured to output an amplified RF signal. The RF amplifier architecture can further include a first feedback circuit implemented between the drain of the second FET and the gate of the second FET to provide gain control, and a second feedback circuit implemented between the drain of the second FET and the gate of the first FET to provide an increase in a frequency range having a desirable range of gain.

Abstract: A method in a memory device implementing error correction includes setting an error correction event register to a first value; accessing a memory location in the first memory array in response to a memory address; retrieving stored memory data from the accessed memory location in the first memory array and retrieving error correction check bits corresponding to the accessed memory location from the second memory array; checking the retrieved memory data for bit errors using the retrieved check bits; in response to a bit error being detected in the retrieved memory data, generating corrected memory data using the retrieved check bits and asserting an error correction event signal; and in response to the error correction event signal being asserted, setting the error correction event register to a second value.

Abstract: A bushing allows for adjustability of a position of a headrest. The bushing includes a head portion having an opening and a passageway opening. The bushing also includes a body portion defining an internal passageway. The passageway opening of the head portion is aligned with the internal passageway of the body portion. The body portion includes a wall surrounding an area of reduced thickness, and a protrusion is located on an internal surface of the area of reduced thickness. The bushing also includes a moveable portion received in the opening of the head portion. The moveable portion is moveable between a first position where a feature engages a notch of a post receivable in the internal passageway of the body portion and the passageway opening of the head portion to retain the headrest in a position and a second position where the feature is disengaged from the notch of the post, allowing the post and the headrest to move relative to the bushing.

Abstract: A flash memory device employs a low current auto-verification programming scheme using multi-step programming voltage and cell current detection. The low current auto-verification programming scheme performs programming of memory cells by the application of programming voltages in step increments. For each programming pulse, the cell current of the memory cell is sensed to determine when the memory cell is programmed. The programming pulse is terminated when the cell current decreases below a reference current level.

Abstract: A flash memory device implements a sequential read method using overlapping read cycles to initiate the bit-line precharge and equalization operation for a next memory cell address prior to the completion of the read cycle of the current memory cell address. More specifically, the sequential read method implements overlapping read cycle where the bit-line precharge and equalization operation is started for a memory cell of the next address while the memory cell of the current address is being read out. In this manner, the read speed for the sequential read operation of the flash memory device is improved. In some embodiments, the memory cell array for each input-output (I/O) of the flash memory device is partitioned into two sub-banks to further reduce the read cycle time by enabling early activation of the word-line for the next sub-bank.

Abstract: A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the selective refresh operation introduces a sense margin guardband so that a memory cell having programmed resistance that falls within the sense margin guardband will be refreshed during the read operation. The selective refresh operation is performed transparently at each read cycle of the memory cells and only memory cells with reduced sense margins are refreshed.

Abstract: Disclosed an apparatus and method of partitioning compressed satellite image, and more specifically, the present invention relates to a technique for forming index information on the compressed satellite image using the starting point and the length of a compressed section so as to randomly access each compressed section in the wavelet-based compressed satellite image recommended through CCSDS. The present invention minimizes costs for long-term storage of the satellite image data by immediately indexing, partitioning, and storing the compressed satellite data in a storage without recovering the compressed satellite data, rapidly provides high-quality satellite images for users by minimizing information loss while recovering the compressed image, and thereby being effective for being able to reduce computing resources needed to recover the compressed image data.

Abstract: An ophthalmoscope comprises an illumination element providing an illumination light beam to illuminate the fundus of an eyeball; an imaging lens group converging the reflected light beam from the fundus; and an image capture module. The image capture module includes an image sensing element, a fixation light element and an optical element. The image sensing element captures the reflected light beam converged by the imaging lens group to form an image. The fixation light element provides a fixation light beam passing through the imaging lens group and reaching the fundus. The optical element is arranged among the imaging lens group, image sensing element and fixation light element to make the image sensing element and the fixation light element on different equivalent focal planes of the imaging lens group. According to the above-mentioned structure, a relay lens and a focusing module used by the conventional fixation light element is omitted.

Abstract: A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the selective refresh operation introduces a sense margin guardband so that a memory cell having programmed resistance that falls within the sense margin guardband will be refreshed during the read operation. The selective refresh operation is performed transparently at each read cycle of the memory cells and only memory cells with reduced sense margins are refreshed.

Abstract: Resin compositions, layers, and interlayers comprising two or more thermoplastic polymers and at least one RI balancing agent for adjusting the refractive index of at least one of the resins or layers is provided. Such compositions, layers, and interlayers exhibit enhanced optical properties while retaining other properties, such as impact resistance and acoustic performance.

Abstract: A non-volatile memory device includes a two-dimensional array of non-volatile memory cells where a first portion of memory cells being configured as an one-time-programmable memory area; a bypass read-out circuit configured to sense a signal level on a bit line in response to a memory cell in the one-time-programmable memory area being selected and to generate a first signal indicative of the signal level on the bit line; and a trim data latch circuit having an input terminal configured to receive the first signal. The trim data latch circuit is configured to store a signal related to the first signal as a trim data value and to provide trim data value to circuitry of the non-volatile memory device. The trim data value may be applied to adjust a signal level of the circuitry of the non-volatile memory device.

Abstract: A non-volatile memory device includes a sector pass/fail indicator circuit configured to store a pass/fail indicator for each sector in a first block of memory cells. The pass/fail indicator has a first value indicating the respective sector has failed erase verification and has a second value indicating the respective sector has passed erase verification. The sector pass/fail indicator circuit set the respective pass/fail indicators to the second value for one or more sectors in the first block after the respective sectors pass erase verification following a previous block erase operation of the first block. The first block is subjected to subsequent block erase operation where only word lines associated with the sectors having a pass/fail indicator having the first value are biased to the first bias voltage level.