Abstract: A system and its method using waste heat energy to generate useful electricity for mobile projector is revealed; the purpose are two folds: first is to reduce the excessive heat, in order to increase the brightness; the second is to recycle the energy, so to extend the working hours between the recharges. The key component used is silicon based reversible heat pump diode, which can convert the electrical energy to heat energy, or from heat energy to electrical energy. Both hydrophilic and hydrophobic coatings are used to enhance the energy converting efficiency. One sample implementation combined with standard alone battery charger is described in details.

Abstract: A system and its methods using 4D signature to verify ones' online transaction through mobile projector is disclosed for the first time; the purpose is to enhance the security of currently booming e-commence industry. By 4D, we mean a signature that is written in 3D space and 1D time. The speed and the force the writer used are all recorded in great details, and it becomes very hard to be forged. One sample implementation combined with a popular smart phone is described in details. Two mini projectors and two cameras are used in a coordinated way, with one catch even line, and the other catch odd line; and both catch the red green and blue in strictly defined time sequences. Pre-distortion, de-jitter, auto focus and background color compensation methods are also included. Finally, cloud sever is used to improve the authentication accuracy, through the data fusion.

Abstract: A system and its design variations using heat pump to generate useful warm and cool usages for multi functional mobile projector is exposed; the purpose is two folds: first is to reduce the excessive heat, in order to increase the brightness; the second is to reuse the energy, so to extend the functionalities. The key component used is silicon based heat pump, which can convert the electrical energy to heat energy. Different shaped heat or cool fins are designed to match the multiple use cases. One sample implementation using digital serial interface is described in details.

Abstract: A method in a resistive memory device includes configuring two or more memory cells in a column of the array sharing the same bit line and the same source line to operate in parallel as a merged memory cell; programming the resistance of the merged memory cell in response to the write data, the resistance of the two or more resistive memory cells in the merged memory cell being programmed simultaneously; and reading the programmed resistance value of the merged memory cell, the programmed resistance of the two or more memory cells in the merged memory cell being read simultaneously.

Abstract: A circuit for detecting a signal transition on an input signal includes a mirror delay circuit and an input blocking circuit to prevent signal glitches or undesired signal pulses from being passed to the output signal node, thereby preventing signal distortions from being detected as a valid signal transition. The input transition detection circuit generates stable and correct transition detection pulses having a consistent pulse width.

Abstract: A simulation method for simulating a three-dimensional structure, comprises the steps of: discretizing the three-dimensional structure into two-dimensional (“2-D”) layers; constructing a two-dimensional basis for each of the 2-D layers; and constructing a one-dimensional finite difference basis between the 2-D layers.

Abstract: A developing device includes a housing, a development roller, and a roller gear. The roller gear is disposed at one axial end of the development roller and transmits a rotational drive force to the development roller. The development roller includes a sleeve and a coating layer. The coating layer is formed by dipping the sleeve in a dipping bath with the sleeve directed axially vertically. The development roller is mounted to the housing such that a lower axial end of the development roller at the time of the dipping is an opposite axial end to the one axial end at which the roller gear is disposed.

Abstract: A flash memory device uses a pair of parallely connected NMOS transistors with different voltage ratings to generate the reference current for the sense amplifier used in the read out operations. The reference current thus generated is temperature compensated with zero or near-zero temperature coefficient. In some embodiments, the pair of parallely connected NMOS transistors includes a high voltage NMOS transistor and a low voltage NMOS transistor or NMOS transistors with different gate oxide thicknesses.

Abstract: A memory device using error correction code (ECC) implements a memory array parallel read-write method to reduce the storage overhead required for storing ECC check bits. The memory array parallel read-write method stores incoming address and data into serial-in parallel-out (SIPO) address registers and write data registers, respectively. The stored data are written to the memory cells in parallel when the SIPO registers are full. ECC check bits are generated for the block of parallel input data stored in the write data registers. During the read operation, a block of read out data corresponding to the read address are read from the memory cells in parallel and stored in read registers. ECC correction is performed on the block of read out data before the desired output data is selected for output.

Abstract: A computer system, and a computer-implemented method are provided for maintaining, providing and exchanging up to date credentialing information on a member to and from participant organizations. A database is maintained of credentialing information applicable to the member and obtained from credentialing organizations. Updates are managed to the member credentialing information, obtained through electronic network communications and synchronized with the credentialing organizations. The member credentialing information is updated, and synchronized with, participant organization systems of the participant organizations, on an automated basis.

Abstract: A method in a resistive memory device includes configuring two or more memory cells in a column of the array sharing the same bit line and the same source line to operate in parallel as a merged memory cell; programming the resistance of the merged memory cell in response to the write data, the resistance of the two or more resistive memory cells in the merged memory cell being programmed simultaneously; and reading the programmed resistance value of the merged memory cell, the programmed resistance of the two or more memory cells in the merged memory cell being read simultaneously.

Abstract: A resistive memory device incorporates a reference current generation circuit to generate a reference current for the sense amplifier that is immune to variation in the resistance of the reference resistive memory cells. In some embodiments, the reference current generation circuit uses reference resistive memory cells configured in the low resistance state only. The reference current generation circuit generates the reference current by combining a reference cell current and a bias current. The bias current is regulated by a feedback circuit in response to changes in the reference current to maintain the reference current at a substantially constant value and having a current value being an average of the cell currents for a resistive memory cell in the high resistance state and the low resistance state.

Abstract: A method in a memory device implementing error correction includes setting an error correction event register to a first value; assessing a memory location in the first memory array in response to a memory address; retrieving stored memory data from the assessed memory location in the first memory array and retrieving error correction check bits corresponding to the assessed memory location from the second memory array; checking the retrieved memory data for bit errors using the retrieved check bits; in response to a bit error being detected in the retrieved memory data, generating corrected memory data using the retrieved check bits and asserting an error correction event signal; and in response to the error correction event signal being asserted, setting the error correction event register to a second value.

Abstract: A bushing allows for adjustability of a position of a headrest. The bushing includes a head portion having an opening and a passageway opening. The bushing also includes a body portion defining an internal passageway. The passageway opening of the head portion is aligned with the internal passageway of the body portion. The body portion includes a wall surrounding an area of reduced thickness, and a protrusion is located on an internal surface of the area of reduced thickness. The bushing also includes a moveable portion received in the opening of the head portion. The moveable portion is moveable between a first position where a feature engages a notch of a post receivable in the internal passageway of the body portion and the passageway opening of the head portion to retain the headrest in a position and a second position where the feature is disengaged from the notch of the post, allowing the post and the headrest to move relative to the bushing.

Abstract: A device for detecting defective memory includes a first global word line; a second global word line; a global word-line front end, connected to the first global word line; a global word-line driver, connected to the global word-line front end and driving the first global word line; a local word-line driver, connected to the first global word line and driving a local word line; and a voltage-controlled transistor, including a first terminal connected to the first global word line, a second terminal connected to a connection line between the global word-line front end and the global word-line driver, and a third terminal outputting a test current.

Abstract: A non-volatile memory device includes a two-dimensional array of non-volatile memory cells where a first portion of memory cells being configured as an one-time-programmable memory area; a bypass read-out circuit configured to sense a signal level on a bit line in response to a memory cell in the one-time-programmable memory area being selected and to generate a first signal indicative of the signal level on the bit line; and a trim data latch circuit having an input terminal configured to receive the first signal. The trim data latch circuit is configured to store a signal related to the first signal as a trim data value and to provide trim data value to circuitry of the non-volatile memory device. The trim data value may be applied to adjust a signal level of the circuitry of the non-volatile memory device.

Abstract: A flash memory device uses a pair of parallely connected NMOS transistors with different voltage ratings to generate the reference current for the sense amplifier used in the read out operations. The reference current thus generated is temperature compensated with zero or near-zero temperature coefficient. In some embodiments, the pair of parallely connected NMOS transistors includes a high voltage NMOS transistor and a low voltage NMOS transistor or NMOS transistors with different gate oxide thicknesses.

Abstract: A fluid-fillable barrier which includes a flexible, tubular, impermeable membrane and at least two internal tension members. The membrane has opposite ends, a middle, fluid-fillable section, an upper attachment area, and a lower attachment area. The tension members secure between, and extend from, the upper attachment area to the lower attachment area. The tension members have a length which is less than one-half the perimeter of the membrane, the length and perimeter being measured at a common cross-section, taken perpendicular to a longitudinal axis of the membrane. One of the tension members is longer than the other, so that it is in a relaxed, limp state under normal operating conditions. The tension members are thermally bonded to, and sewn with a double sew line to, the attachment areas. The barrier further includes lifting loops at each end, connection cleats on the sides and ends, and venting/drainage standpipes.

Abstract: A flash memory device employs a low current auto-verification programming scheme using multi-step programming voltage and cell current detection. The low current auto-verification programming scheme performs programming of memory cells by the application of programming voltages in step increments. For each programming pulse, the cell current of the memory cell is sensed to determine when the memory cell is programmed. The programming pulse is terminated when the cell current decreases below a reference current level.

Abstract: A turbocharger system comprises a first relatively small high-pressure (HP) turbocharger and a second relatively large low pressure (LP) turbocharger. The turbine of the LP turbocharger is connected in series downstream of the turbine of the HP turbocharger in a first exhaust gas passage. An exhaust bypass flow passage provides a bypass flow path around the HP turbine. A rotary valve is located at a junction of the bypass flow passage and a first exhaust gas flow passage. The rotary valve comprises a valve rotor which is rotatable to selectively permit or block flow to the LP turbine from either the first exhaust gas passage or the bypass gas passage.