Abstract: A non-volatile memory device includes a control circuit configured to perform a block erase operation including a block erase cycle and an erase verify cycle on a block of memory cells. The control circuit is configured to perform the erase verify cycle by storing a last verify address for each sector of the block of memory cells, verifying each memory cell in a sector starting from the last verify address for the sector until a memory cell has failed erase verification in that sector, storing the memory cell address of the failed memory cell as the last verify address for that sector, skipping the erase verification for the remaining memory cells in that sector, and continuing the erase verify cycle at a last verify address for the next sector.

Abstract: A non-volatile memory device includes a sector pass/fail indicator circuit configured to store a pass/fail indicator for each sector in a first block of memory cells. The pass/fail indicator has a first value indicating the respective sector has failed erase verification and has a second value indicating the respective sector has passed erase verification. The sector pass/fail indicator circuit set the respective pass/fail indicators to the second value for one or more sectors in the first block after the respective sectors pass erase verification following a previous block erase operation of the first block. The first block is subjected to subsequent block erase operation where only word lines associated with the sectors having a pass/fail indicator having the first value are biased to the first bias voltage level.

Abstract: An archery bow is described, and which has a resilient, main body having opposite distal ends; a biasing member is borne by the main body; and a string extends, and is tensioned between the distal ends, and wherein the string has a first, at rest position; a second, arrow release position; and a third, string return position, and wherein the biasing member applies a biasing force to resist the movement of the string from the third, string return position, to the first, at rest position, and a biasing force to assist in the movement of the string from the first, at rest position, to the second, arrow release position.

Abstract: A non-volatile memory device includes a sector pass/fail indicator circuit configured to store a pass/fail indicator for each sector in a first block of memory cells. The pass/fail indicator has a first value indicating the respective sector has failed erase verification and has a second value indicating the respective sector has passed erase verification. The sector pass/fail indicator circuit set the respective pass/fail indicators to the second value for one or more sectors in the first block after the respective sectors pass erase verification following a previous block erase operation of the first block. The first block is subjected to subsequent block erase operation where only word lines associated with the sectors having a pass/fail indicator having the first value are biased to the first bias voltage level.

Abstract: A low voltage bandgap reference circuit includes a positive temperature coefficient circuit unit, a negative temperature coefficient circuit unit and a load unit, wherein the positive temperature coefficient circuit unit comprises a first differential operational amplifier, a first, second and third transistor, a first resistor, a first and second diode, and the negative temperature coefficient circuit unit includes a second differential operational amplifier, a fourth, fifth and sixth transistor, a second resistor and a third diode. The low voltage bandgap reference circuit provides a current having a positive temperature coefficient characteristics and a current having a negative temperature coefficient characteristics to flow through the load in order to generate a stable reference voltage less affected by the temperature. Therefore, it avoids the problems of the low voltage bandgap reference circuit that can not be activated at low voltage.

Abstract: A medical imaging system includes a first lens set, a light source and an image forming module. The medical imaging system of the present invention configures the light source according to the object-image relationship of lens, so that illuminating light may sufficiently enter a cavity, significantly increasing the luminous efficiency. Also, the image forming and illuminating components are integrated into one system, thereby achieving advantages of reduced volume and cost saving.

Abstract: A memory erasing method and a driving circuit thereof are introduced, when cells are selected to be erased, the method includes setting gates of cells which are not selected to be erased and are located at a selected block, drains of all the cells in a selected bank, and the gate of the unselected cells to be floating; supplying a positive voltage to all the sources in a selected bank and their shared P well and N well; and supplying a negative voltage to the gates of the cells located in a selected block and selected to be erased. Accordingly, a positive coupling voltage from P wells is received whenever gates are floating, so as to inhibit erasure of unselected blocks and thereby streamline decoding, thus making it easy to attain further expansion of blocks or banks with a small layout area and partition of sectors in the blocks.

Abstract: A method to trim a reference voltage source formed on an integrated circuit includes configuring the integrated circuit in a test mode; providing a power supply voltage and a trim code sequence to the integrated circuit where the power supply voltage is provided by a precision reference voltage source; generating a target voltage on the integrated circuit using the power supply voltage; generate a reference voltage using the reference voltage source formed on the integrated circuit; applying one or more trim codes in the trim code sequence to the reference voltage source to adjust the reference voltage; comparing the reference voltage generated based on the trim codes to the target voltage; asserting a latch signal in response to a determination that the reference voltage generated based on a first trim code is equal to the target voltage; and storing the first trim code in response to the latch signal being asserted.

Abstract: A method of identifying a damaged bitline address in a non-volatile memory device is introduced. The non-volatile memory device includes a memory cell array and a plurality of bit lines crossing the memory cell array. Each bit line has a first end and a second end. The bit lines are divided into a first group and a second group. The method includes applying a source voltage (charging) or ground voltage (discharging) to a specific group of bit lines, testing the bit lines in two testing stages (open-circuit testing and short-circuit testing) by the principle that no damaged bit line can be charged or discharged, and acquiring an address data of a damaged bit line according to a status data stored in a page buffering circuit and related to whether a bit line is damaged, thereby dispensing with a calculation process for estimating the address of the damaged bit line.

Abstract: A circuit for detecting a signal transition on an input signal includes a mirror delay circuit and an input blocking circuit to prevent signal glitches or undesired signal pulses from being passed to the output signal node, thereby preventing signal distortions from being detected as a valid signal transition. The input transition detection circuit generates stable and correct transition detection pulses having a consistent pulse width.

Abstract: A high-speed data transmission structure includes first and second electronic units and an input/output bus. The input/output bus is electrically connected to the first and second electronic units, and includes a clock signal line and N data lines, where N is an even integer. The data lines are divided into first and second data signal line groups, each provided with the same number of data lines. In a transmit mode, the first electronic unit generates and transmits a clock signal to the clock data line, and generates output signals at each clock period of the clock signal. The output signals consist of N/2 data signals lasting for two clock periods of the clock signal, and the first and second data signal line groups alternatively receive the output signals. The second electronic unit simultaneously performs a receive mode to fetch and latch the data signals according to the clock signal.

Abstract: Disclosed an apparatus and method of partitioning compressed satellite image, and more specifically, the present invention relates to a technique for forming index information on the compressed satellite image using the starting point and the length of a compressed section so as to randomly access each compressed section in the wavelet-based compressed satellite image recommended through CCSDS. The present invention minimizes costs for long-term storage of the satellite image data by immediately indexing, partitioning, and storing the compressed satellite data in a storage without recovering the compressed satellite data, rapidly provides high-quality satellite images for users by minimizing information loss while recovering the compressed image, and thereby being effective for being able to reduce computing resources needed to recover the compressed image data.

Abstract: A request is received from an insured member to process a claim for an incident. One or more specific insurance policies for the insured member are retrieved from a database and claim rules for each policy are retrieved from the database, producing one or more claim rules for the insured member. One or more claim questions are generated specifically for the insured member based on the one or more claim rules. One or more claim questions are sent to the insured member regarding an incident. One or more responses are received from the insured member in response to the one or more claim questions. One or more claim forms of the one or more specific insurance policies are selected based on the one or more responses and the one or more claim rules. The one or more claim forms are filled out based on the one or more responses.

Abstract: A commercial steam-cleaning laundry machine is configured to use steam instead of dry-cleaning chemicals or water as a primary cleaning agent for garments rotating in a drum of the commercial steam-cleaning laundry machine. In one embodiment of the invention, a steam injector at least partially exposed to an inner surface of the drum is configured to provide a MCU-controlled fresh steam injection into the drum during a cleaning cycle of the commercial steam-cleaning laundry machine. The fresh steam into the commercial steam-cleaning laundry machine is from an outtake of a standalone boiler system which is typically used for a variety of fabric treatment machines in a commercial laundry operation. A debris and clean steam/air separation chamber periodically or continuously separates and/or filters debris, chemicals, and/or other undesirable elements from the drum and evacuates clean or cleaned-up air and moistures to au air-out duct.

Abstract: A lens module comprises a first lens group, a second lens group and a third lens group, which are arranged from an eye fundus side to an image side in sequence. The first lens group has a positive effective focal length (EFL) and includes a first lens having two convex surfaces respectively facing the eye fundus side and the image side. The second lens group has a positive or negative EFL and includes a plurality of second lenses, wherein the second lens closest to the eye fundus side has a concave surface facing the eye fundus side. The third lens group has a positive EFL and includes a plurality of third lenses, wherein at least one third lens is a cemented lens. The abovementioned lens module decreases the volume of a lens module and reduces the ghosting effect. An eye fundus camera using the abovementioned lens module is also disclosed.

Abstract: A low voltage bandgap reference circuit includes a positive temperature coefficient circuit unit, a negative temperature coefficient circuit unit and a load unit, wherein the positive temperature coefficient circuit unit comprises a first differential operational amplifier, a first, second and third transistor, a first resistor, a first and second diode, and the negative temperature coefficient circuit unit includes a second differential operational amplifier, a fourth, fifth and sixth transistor, a second resistor and a third diode. The low voltage bandgap reference circuit provides a current having a positive temperature coefficient characteristics and a current having a negative temperature coefficient characteristics to flow through the load unit, whereby generate a stable reference voltage thereon, which the stable reference voltage is less affected by the temperature. Therefore, it avoids the problems of the low voltage bandgap reference circuit can not be activated at low voltage.

Abstract: A semiconductor device and a method for accelerating erase verification process thereof are introduced, in which a correction unit of erase verification is connected between broken bit lines of the semiconductor device and a page buffer. Grounding switches in the correction unit of erase verification are allowed to connect the broken bit lines to ground during an erase verification process by means of a specific circuit arrangement with respect to the broken lines. Thereby, the earth voltage is received, and further, that the broken bit lines pass the erase verification is identified by the page buffer, further saving time consumed in repeated verifications in the conventional technology significantly.

Abstract: A non-volatile memory having discrete isolation structures and SONOS memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory.

Abstract: A liquid extraction assembly for extracting liquid from a mass comprising a housing having an inlet and an outlet and a path therebetween. The housing includes a rotating screen adjacent the path. The housing can have a nozzle at the inlet. The housing can include an inflatable member providing a seal adjacent the screen for maintaining the mass in the path. The housing can include a center seal rotating with the screen and a fixed scraper in the path and adjacent the at least one rotating screen, with the center seal including a notch for accepting a tip of the scraper therein. The housing can also include side walls and an annular seal located between the side walls, with the annular seal defining an outer periphery of the path and having a rotating top end portion allowing an area of the outlet to change.

Abstract: In a local word line driver of an NOR flash memory and its flash memory array device, the local word line driver is provided for driving a local word line in a sector of a memory array, and the local word line driver has two transistors including a first transistor and a second transistors, and the first and second transistors are NMOS transistors, and thus achieving the effects of reducing the area occupied by circuits on the local word line driver and the die size, and saving the area for the use by memory units.