Abstract: An apparatus for interfacing materials and absorbing disparate thermal expansions thereof utilizes a woven wire mesh to support a predetermined thickness of a first soft solder which absorbs expansions, and utilizes a second soft solder having a lower melting point than the first to coat the surfaces of the wire mesh/first soft solder combination so that the materials can be bonded thereto.

Abstract: This invention is a device to reduce the wobble of a rotating shaft disposed in a cavity of a housing which wobble results from a spurious or undesirable positioning of a bearing assembly in which the shaft rotates. The present device includes a bearing follower which is shaped to have a long side which is in abutment with the side walls of the cavity. Accordingly, the follower cannot be readily placed in a cocked or misaligned position. The follower is spring loaded against the bearing assembly which is subject to being cocked and thereby reduces the capability of that bearing assembly to be misaligned.

Abstract: In a hierarchical memory system, replacement of segments in a cache memory is governed by a least recently used algorithm, while trickling of segments from the cache memory to the bulk memory is governed by the age since first write. The host processor passes an AGEOLD parameter to the memory subsystem and this parameter regulates the trickling of segments. Unless the memory system is idle (no I/O activity), no trickling takes place until the age of the oldest written-to segment is at least as great as AGEOLD. A command is generated for each segment to be trickled and the priority of execution assigned to such commands is variable and determined by the relationship of AGEOLD to the oldest age since first write of any of the segments. If the subsystem receives no command from the host processor for a predetermined interval, AGEOLD is ignored and any written-to segment becomes a candidate for trickling.

Abstract: A run-length-limited group coding system is provided wherein the code permits a high data transfer efficiency. Code values for both data and control functions are chosen such that the maximum cumulative DC deviation from a nominal center is no more than 10 percent averaged over a data transmission sequence. The code employed limits the maximum number of zero bits between successive one bits in a serial binary sequence to a predetermined value thereby permitting self-clocking. The coding system is particularly suitable for use in baseband data transmission systems where the transmission medium is either an electrical or optical link. Code values for control functions meet the same constraints as those for data and protocols are established such that the coding system may be integrated into a variety of multiple-unit system configurations wherein the communication between units is, for example, by way of a point-to-point link, or a bus, star, loop, or ring arrangement.

Abstract: In a data processing system including a processor, a bulk memory, a cache, and a storage control unit for controlling the transfer of data between the bulk memory and the cache, a timestamp is generated with each write command. A linked list is maintained, having an entry therein corresponding to each segment in the cache which has been written to since it was moved from the bulk memory to the cache. The timestamp accompanying a write command which is the first command to write to a segment after that segment is moved from bulk memory to the cache is entered into the list at the most recently used position. An entry in the linked list is removed from the list when the segment corresponding thereto is transferred from the cache to the bulk memory. The linked list is utilized to update a value TOLDEST, which represents the age of the oldest written-to segment in the cache that has not been returned to bulk memory since it was first written to.

Abstract: A power failure protector circuit prevents spurious output signals from an electronic circuit when power to the electronic circuit is interrupted. The output of the electronic circuit is effectively blocked by a switch. The switch is turned off when the power supply is turned on and remains off until the power supply is interrupted. A capacitor is normally charged to the operating voltage of the power supply and when the power supply is interrupted, the capacitor discharges to turn the switch on during the interval when the operating voltages of the electronic circuit are decaying. The capacitor also provides a power source to maintain the operating voltages of the electronic circuit near normal for a short interval after the power supply is interrupted thus insuring correct operation of the electronic circuit until after the switch is turned on and the output from the circuit is blocked.

Abstract: A lateral flotation mechanism for the header on a combine harvester is disclosed wherein a pair of springs provide a counterbalancing force to stabilize the pivotal movement of the header about a centrally disposed pivot from externally imposed loads. After the external load is removed from the header, the springs effect a rotation of the header about the center pivot to return the header to a predetermined stabilized position. The compression of the springs is adjustable to pre-load the springs and compensate for any imbalance in the header.

Abstract: A skid steer loader having transversely spaced wheel assemblies driven through a drive chain entrained around a tensioning idler is disclosed wherein the tensioning idler is mounted in a pair of arms movably positionable by an adjusting mechanism to control the tension in the drive chain. The adjusting mechanism is housed within a box welded to the chain case and includes a necked down portion extending through the box for external manipulation of a drive portion. An O-ring seal prevents the loss of fluid from the box during operation of the loader. A spring clip engagable with the drive portion of the adjusting mechanism prevents the movement thereof during operation of the loader.

Abstract: A multi-position return to center potentiometer having a multiple detent configuration wherein the center detent position is a dimple and other detent positions provide a resistance to rotation that is greater during rotation away from center than rotation toward the center allowing the use of a small return to center spring.

Abstract: A method and a means are disclosed for the throughchecking of the normalizer operations of an arithmetic unit of a data processing system involving both integer and floating-point formats in single and double precision operations. A post normalizer is used in conjunction with the main normalizer of the arithmetic unit to determine if the result is indeed normalized. Where the post normalize count is zero, an error designator remains inactivated. However, where the count is non-zero, the error designator is activated to indicate an error exists, unless it is disabled by separate circuitry which detects that the number being shifted is .+-..0.. The preferred embodiment disclosed herein checks the operation of a pair of 72-bit main normalizers with a single 13-bit post normalizer. A plurality of instructions in which this check is significant are illustrated.

Abstract: A unique memory management system for use with a memory device which is common (or shared) with a plurality of user elements utilizing a memory address counter, scratch pad address memory, external memory address inputs and an address multiplexer.

Abstract: An improved dynamic memory system including through-checking and error detection of the refresh counter is described. A refresh counter that provides parity of the refresh count for through-checking, of refresh addresses is shown. Error detecting circuitry is utilized in conjunction with the refresh counter and the parity generating circuitry to detect errors in functionality of the refresh counter. The refresh counter is a Gray code counter constructed of a double rank of latches operable with code generating logic circuits for determining the sequence of generation of Gray code groupings.

Abstract: In a baler having a duct communicating at one end with an inlet opening formed in a bale case, a feeder mechanism is provided to pack crop material into the duct and to stuff crop material from the duct into the bale case via the inlet opening. The feeder mechanism includes a first set of feeder elements arranged so that their outer ends follow a first path of movement and a second set of feeder elements arranged so that their outer ends follow a second path of movement. The first and second paths of movement are generally apple-shaped and are offset relative to each other.

Abstract: A clock source for timing and synchronizing the operation of digital data processing equipment and having automatic duty cycle correction is described. A source of signals provides clock signals at a predetermined frequency. A buffer circuit provides the true and complement clock signals to low pass filters that function to filter the true and complement clock signals to DC levels proportional to the duty cycle of the source signals. The DC voltages represent instantaneous deviation voltages from a known reference and are applied to a differential amplifier circuit for providing a feedback signal for adjusting the duty cycle of the clock output pulses that are available. One embodiment has the source of signals directly coupled to the buffer circuitry and utilizes the feedback signal to adjust the duty cycle of the signal source circuitry. A second embodiment has the source signals capacitively coupled to the self-correcting circuitry and the feedback signals adjust the duty cycle of the clock output signal.

Abstract: The adjustment of operating parameters such as the sieve opening, concave opening, chaffer opening, rotor speed and/or fan speed is/are accomplished under the control of a microprocessor operating in response to the striking of keys on a keyboard. The combine harvester operator may select a particular parameter for adjustment by striking a key corresponding to that parameter. The desired setting of the selected parameter is then keyed into the keyboard and an ADJUST key struck to activate the adjustment process. Alternatively, the operator may strike a key corresponding to the crop to be harvested, a further key corresponding to the ambient moisture level of the crop, and then the ADJUST key. In this case the microprocessor reads from a stored table the values for adjusting all parameters so as to obtain a satisfactory sample and a maximum yield for the crop being harvested.

Abstract: Dynamic behavior of structures subject to vibrations is monitored with light coupled into a single multi-mode optical fiber positioned within or on the structure. Vibration caused strain or deflections in the structure are detected by interference light signal intensity variations caused by differential phase changes in the transmission modes. These intensity variations are optically detected to provide an electrical output. Actuators may be positioned at the vibration nodes of the structure and energized by signals derived from the electrical output signals to suppress the vibrations.

Abstract: A multiplexing apparatus for outputting selected input signals utilizes input transistors coupled between input sources and diodes. A first set of switching transistors, coupled to the input transistors and the diodes, blocks the outputting of nonselected input signals by applying a predetermined voltage to the anodes of corresponding diodes. A second set of switching transistors, coupled to the input transistors and the diodes, permits the outputting of selected input signals on the emitters of output transistors coupled to the diodes, by applying current to the emitters of corresponding input transistors, and the anodes of corresponding diodes.

Abstract: Line patterning apparatus for use with a vector generator comprises a memory storing a plurality of addressable line pattern bit strings. Each string comprises a series of ones and zeros defining a predetermined pattern of dots and/or dashes. Associated with each pattern string is a pattern restart string defining the length of the pattern. The bits of an addressed pattern string and the associated pattern restart string are serially provided by the memory in response to an addressing counter. The bits of the pattern string are utilized for video inhibition to superimpose the pattern on a vector being generated. The bits of the pattern restart string are utilized to clear the counter when a preset restart bit is encountered in the string by the counter.

Abstract: In a system having a cache memory and a bulk memory, and wherein a command queue is maintained for storing commands waiting to be executed, each command is assigned a priority level for execution vis-a-vis other commands in the queue. Commands are generated for transferring from the cache memory to the bulk memory segments of data which have been written to while resident in the cache memory. Each generated command may be assigned a generated priority level which is dependent upon the number of segments in the cache memory which have been written to but not yet copied into the bulk memory. A second priority level may be generated which is dependent on the time which has elapsed since the first write into any of the cache memory segments, and the priority level assigned to any given generated command is the higher of the two generated priority levels.

Abstract: A temperature stable apparatus for mounting an arcuate glass enclosed electrolytic bubble gravity sensor utilizes epoxy cement having a low temperature coefficient of expansion for bonding an end face of a post having a temperature coefficient of expansion equal to that of glass to the center of the glass enclosure of the sensor, and the other end of the post to the center of a rectangular aluminum plate, such that the longitudinal axis of the post is orthogonal to the plate and the plane of the arcuate axis of the enclosure, and such that a chord connecting the ends of the arcuate axis is parallel to the longitudinal axis of the plate.