Abstract: A method of manufacturing a Magnetic Tunnel Junction (MTJ) device including pillar contacts coupling the free magnetic layer of MTJ pillars to a top contact. The pillar contacts are electrically isolated from one or more other portions of the MTJ pillar by one or more self-aligned sidewall insulators. The MTJ device further including one of a static magnetic compensation layer or an exchange spring layer in the MTJ pillar.

Abstract: Dynamic redundancy buffers for use with a device are disclosed. The dynamic redundancy buffers allow a memory array of the device to be operated with high write error rate (WER). A first level redundancy buffer (e1 buffer) is couple to the memory array. The e1 buffer may store data words that have failed verification or have not been verified. The e1 buffer may transfer data words to another dynamic redundancy buffer (e2 buffer). The e1 buffer may transfer data words that have failed to write to a memory array after a predetermined number of re-write attempts. The e1 buffer may also transfer data words upon power down.

Abstract: A method for manufacturing a magnetic memory element for use in a magnetic random access memory device to form a MgO spin current coupling layer with improved spin current coupling and reduced device area resistance (RA). The method involves depositing a magnetic free layer structure, and then depositing a MgO spin current coupling layer over the magnetic free layer. The magnetic spin current coupling layer is deposited in a sputter deposition chamber using radio frequency (RF) power. The sputter deposition of the spin current coupling layer can be performed using a MgO target without intervening oxidation steps to form a continuous layer of MgO that is not a multilayer structure of Mg and intermittent oxidation layers. Because the MgO spin transport layer deposited by this RF sputtering does not affect RA of the device, the thickness of the MgO spin transport layer can be adjusted to optimize spin transport performance.

Abstract: A device includes an array of memory cells, input/output lines coupled to the memory cells, and sense amplifiers coupled to the input/output lines. Each sense amplifier is associated with a respective input/output line. The device also includes trim circuits. Each trim circuit is associated with and coupled to a respective sense amplifier. Each sense amplifier receives a respective reference voltage that allows the sense amplifier to sense a bit value of an addressed memory cell. Each trim circuit is operable for compensating for variations in the reference voltage used by the respective sense amplifier.

Abstract: A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method further comprises writing a second plurality of data words and associated memory addresses into a cache memory, and wherein each data word of the second plurality of data words is associated with a pending operation. Additionally, the method comprises detecting a power up signal and responsive to the power up signal, transferring the second plurality of data words and associated memory addresses from the secure memory storage area to the cache memory. Finally, responsive to the transferring, and before the memory device is powered up, the method comprises processing the second plurality of data words and associated memory addresses from the cache memory to the pipeline for writing data to the memory bank during power up.

Abstract: A Magnetic Random Access Memory apparatus device having a memory element formed as a magnetic tunnel junction (MTJ) pillar and having a heating element for maintaining a desired minimum temperature of the memory element. The heating element is separated from the memory element by a thin, non-magnetic, electrically insulating wall, which can be constructed of alumina. The heating element is connected with circuitry that controllably delivers electrical current to the heating element to maintain a desired minimum temperature of the memory element.

Abstract: Methods and structures useful for magnetoresistive random-access memory (MRAM) are disclosed. The MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes an in-plane polarization magnetic layer and a perpendicular MTJ in conjugation with a alternating current precharge and a programming current pulse that comprises an alternating perturbation frequency and a direct current.

Abstract: According to one embodiment, an apparatus includes a bottom electrode layer positioned above a substrate in a film thickness direction, a source layer positioned above the bottom electrode layer in the film thickness direction, an impact ionization channel (i-channel) layer positioned above the source layer in the film thickness direction, a drain layer positioned above the i-channel layer in the film thickness direction, an upper electrode layer positioned above the drain layer in the film thickness direction that forms a stack that includes the bottom electrode layer, the source layer, the i-channel layer, the drain layer, and the upper electrode layer, and a gate layer positioned on sides of the i-channel layer along a plane perpendicular to the film thickness direction in an element width direction. The gate layer is positioned closer to the drain layer than the source layer. Other apparatuses are described in accordance with more embodiments.

Abstract: A method, according to one embodiment, includes: forming an annular cylindrical channel from a single block of electrically conductive material; forming an oxide layer over exposed surfaces of the annular cylindrical channel and exposed surfaces of the block of electrically conductive material; removing a portion of the oxide layer from an exterior base of the annular cylindrical channel, thereby forming a source contact recess which surrounds the base of the annular cylindrical channel; ion-implanting the exposed electrically conductive material substrate at a base of the source contact recess; and depositing a silicide material in the source contact recess, thereby forming a source contact tab.

Abstract: According to one embodiment, an apparatus includes: a substrate, an array of 3D structures, where each 3D structure includes a source region having a first conductivity, a series of layers positioned in a vertical direction, a channel material on a surface of at least one sidewall of each 3D structure, and a gate dielectric material on the channel material. The series of layers includes a dielectric layer positioned above the substrate, a plurality of a set of MTJ layers positioned above the dielectric layer, and a buffer layer positioned in between the dielectric layer and each set of MTJ layers thereof. The magnetic memory device further includes an isolation region positioned between the 3D structures and at least one gate region positioned above the isolation region, where each gate region is coupled to at least one sidewall of each 3D structure.

Abstract: In accordance with one embodiment, a method includes forming a cleavable donor substrate, the substrate including monocrystalline Si, forming a dielectric layer above the substrate in a film thickness direction, and cleaving the substrate into an upper portion having the dielectric layer and a lower portion. In one embodiment, the cleavable substrate is formed using a sacrificial buffer layer above the substrate in the film thickness direction, and forming a strained Si layer above the sacrificial buffer layer in the film thickness direction, followed by etching away the sacrificial buffer layer to cleave the substrate. In another embodiment, the cleavable substrate is formed by implanting ions into the substrate to a peak implant position located below an upper surface of the substrate, annealing the substrate and dielectric layer in an inert environment to form blisters at the peak implant position, and cleaving the substrate using the blisters.

Abstract: A magnetic storage device is provided. The magnetic storage device comprises a magnetic memory cell, which includes two or more magnetic tunnel junctions (MTJs), including a first MTJ having a first magnetic characteristic and a first electrical characteristic and a second MTJ has a second magnetic characteristic and a second electrical characteristic, wherein the first magnetic characteristic is distinct from the second magnetic characteristic. The magnetic memory cell further comprises a bottom electrode and a top electrode, wherein the two or more MTJs are arranged between the top and bottom electrode in parallel with respect to each other. The magnetic storage device further comprises readout circuitry coupled to the bottom electrode or the top electrode of the magnetic memory cell and write circuitry coupled to the bottom electrode or the top electrode of the magnetic memory cell.

Abstract: A switching device, according to one embodiment, includes: a cylindrical pillar; an annular cylindrical oxide layer which encircles a portion of the cylindrical pillar; an annular cylindrical gate contact which encircles a portion of the annular cylindrical oxide layer; and a source contact which encircles a portion of the cylindrical pillar toward a first end of the cylindrical pillar. Other systems are also described in additional embodiments herein which provide various different switching devices having improved components including improved cylindrical gate contacts, improved source contacts, and/or improved drain contacts. These improved systems and components thereof may be implemented in vertical transistor structures which also include the aforementioned cylindrical pillar and cylindrical gate contact in comparison to conventional surface transistor structures.

Abstract: A method of forming a cylindrical vertical transistor; the method, according to one embodiment, includes: forming a cylindrical pillar from a single block of silicon, forming an oxide layer over an exterior of the cylindrical pillar and exposed surfaces of the block of silicon, coating the oxide layer with a spin-on-glass (SOG), depositing a source mask over a majority of the SOG coating, and removing a portion of the SOG coating and underlying oxide layer, where the portion removed is defined by the source mask. Other systems and methods are also described in additional embodiments herein which provide various different improved processes of forming the cylindrical gate contacts, the source contacts, and/or the drain contacts for vertical transistor structures which also include the aforementioned cylindrical pillar channel structures and cylindrical gate in comparison to conventional surface transistor structures.

Abstract: An advantageous write verify operation for bipolar memory devices is disclosed. The verify operation is performed under the same bias conditions as the write operation. Thus, the verify operation reduces disturb conditions caused when verify operation is performed in opposite bias to write operation. The advantageous write verify operation may be performed with control logic on source and bit lines. In another embodiment, the advantageous write operation is performed with mux coupled to control logic. The mux determines whether verify (0) or verify (1) operation should be performed based on data in a program latch. Moreover, the mux may select bias conditions for read operations based on a register bit. Trim circuits optionally provide guard banding and modify reference voltages for verify operations performed in opposite polarity to normal read operation.

Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. The MRAM device includes a perpendicular magnetic tunnel junction device having a reference layer, a free layer, and a precessional spin current magnetic layer. A skyrmionic enhancement layer is provided adjacent to the free layer. The skyrmionic enhancement layer helps to initiate the switching of the free layer.

Abstract: According to one embodiment, a method includes forming an etch-stop layer above a substrate, forming a matrix layer above the etch-stop layer, forming a set of pillars above the matrix layer, the set of pillars having a predefined spacing therebetween along a plane in an element width direction and an element depth direction, the plane being normal to a film thickness direction, forming a functionalization layer above the pillars, along sides of the pillars, and above the matrix layer, forming first diblock copolymer layers above the functionalization layer, the first diblock copolymer layers self-segregating into a first polymer and a second polymer in a first pattern, removing the first polymer from the first diblock copolymer layers to create a first mask layer, and removing portions of the matrix layer to expose portions of the etch-stop layer positioned therebelow and create a second pattern in the matrix layer.

Abstract: The various implementations described herein include methods, devices, and systems for operating magnetic memory devices. In one aspect, a magnetic memory device includes: (1) a core; (2) a plurality of layers that surround the core in succession; (3) a first input terminal coupled to the core and configured to receive a first current, where: (a) the first current flows radially from the core through the plurality of layers; and (b) the radial flow of the first current imparts a torque on, at least, a magnetization of an inner layer of the plurality of layers; and (4) a second input terminal coupled to the core and configured to receive a second current, where: (i) the second current imparts a Spin Hall Effect (SHE) around a perimeter of the core; and (ii) the SHE contributes to the torque imparted on the magnetization of the inner layer by the first current.

Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. The MRAM device includes a perpendicular magnetic tunnel junction device having a reference layer, a free layer, and a precessional spin current magnetic layer. The precessional spin current magnetic layer has a non-uniform moment density, and may have a moment density at its center that is greater than a moment density at its perimeter. The device is designed to provide control over the injection of stray fields and the electronic coupling between the precessional spin current magnetic layer and the free layer. Switching speed, switching current, and thermal barrier height for the device can be adjusted. The decreased moment density at the perimeter of the precessional spin current layer helps to stabilize the free layer when the effective magnetic field of the precessional spin current layer is high. Spin accumulation can be increased near the center of the precessional spin current layer, helping to switch the free layer.

Abstract: The various implementations described herein include methods, devices, and systems for performing operations on memory devices. In one aspect, a memory device includes: (1) a magnetic memory component; and (2) a current selector component coupled to the magnetic memory component, the current selector component including: (a) a first transistor having a first gate with a corresponding first threshold voltage; and (b) a second transistor having a second gate with a corresponding second threshold voltage, distinct from the first threshold voltage; where the second transistor is coupled in parallel with the first transistor.