Abstract: Method for decrypting, within a wireless communication device, a sequence of encrypted packets received via a wireless communication channel between the communication device and a cell assigned to this device, comprising for each packet the following steps: —the computation of an encrypting sequence corresponding to the packet (21); and —the decrypting of the packet with the aid of the said encrypting sequence (22). In this method, the encrypting sequences are computed before the reception of the packets while the reception quality is above a threshold (20, TH) and an indication of change of cell is not received (24).

Abstract: A composite electronic circuit assembly comprises two MOS or CMOS circuit dice (100, 200) superimposed inside a package. Different modules of the circuit assembly are distributed between the two dice based on the digital, analog, or hybrid nature of said modules. Such a distribution makes it possible to group together the digital modules of the circuit assembly in one of the die and the analog or hybrid modules in the other die. The production cost, development time, and electrical energy consumption of the circuit assembly may thus be reduced.

Abstract: The invention relates to a radio-frequency circuit comprising: —a control unit; and —a phase-locked loop; wherein the control unit is arranged to determine an offset between an actual value of a reference frequency at the input to the loop on the basis of a measurement of the signal output from the filter of the loop, and a theoretical value of said frequency known to the control unit, via a relation known to the control unit, and to control a correction of said offset.

Abstract: An audio amplification circuit is provided having an amplifier that receives an input signal, an output, and a digital control input for receiving a control value in a number n of bits; a comparator having a first input that receives the amplifier's output signal image, a second input that receives a reference potential, and an output; and a thermometer counter having a selection input coupled to the comparator output, and an output delivering an n-bit digital value to the amplifier control input. The amplifier comprises a differential input stage having a first and a second differential branch, each traversed by a bias current, the current in the first branch being modifiable by n basic current sources which each deliver either a current identical for all current sources, or no current, as a function of one respective bit of the digital control value received at the control input.

Abstract: The method disclosed herein is implemented in a radio receiver to detect an AWGN channel, where the radio receiver comprises a rake receiver. The radio receiver receives signals transmitted via a propagation channel from a transmitter, and determines that the propagation channel is an AWGN channel when a filtered version of a minimum value of a metric is lower than a threshold value. The metric relates to a difference between a normalized measured power profile of the propagation channel and a normalized power template, which normalized power template is dependent on predetermined sampling timing shifts and on rake finger positions within the rake receiver.

Abstract: A matrix for use with a radio transceiver having at least two signal sources is provided. The matrix comprises for each selected set of two or more signal sources, a list of combinations of harmonics of the signal sources, the combinations of harmonics each having a predicted amplitude greater than a predetermined threshold, and a frequency within a defined range related to a frequency range of one of the signal sources. Further, methods for generating such matrix and methods for avoiding spurs are provided.

Abstract: The invention concerns a Near Field Communication method comprising a step (1) of generating, by an antenna of a transmitter, a magnetic field (H), a step (2) of receiving, by an antenna of a tag, power from said generated magnetic field (H), then causing a drop in said generated magnetic field (H), wherein said method further comprises a step (3) of estimating said drop by sensing a voltage swing across said transmitter antenna.

Abstract: Method for controlling a data transfer on a serial transmission data transfer bus by means of a central processing unit and associated system. The method includes various steps, including determining an available bandwidth for a data bus, determining an available computing capacity percentage of the central processing unit, and determining a maximum data rate that a data transfer can be performed on the data bus based on the available bandwidth and the available computing capacity percentage. Furthermore, the method provides that the data transfer rate is controlled to not exceed the maximum data rate.

Abstract: A component of an electronic circuit, the component comprising: a node (REG_ENB; DO) selectively configurable as an output node for providing an output signal to an external component or as an input node for providing an input signal to an internal component; a capacitor (C) selectively coupled to the node (REG_ENB; DO) to influence the time for the node (REG_ENB; DO) to transition between a low state and a high state; and a timer for measuring the time for the node to transition between a low state and a high state to provide a first information input signal, the state of the first information signal depending on the time for the node to transition between the low state and the high state and being indicative of a first information. A method of node management is also described.

Abstract: A digital class D amplifier (10) is disclosed, comprising a pulse width modulator (PW Mod) comprising: a digital loop filter (Loop F) adapted to receive an input signal (x[n]) and a feedback signal (fb[n]), the digital loop filter (Loop_F) being adapted to process at a clock frequency (f_s) said input and feedback signals for providing as output a filtered digital signal (w[n]); a PWM conversion module (PW_CM) having an input (24) for receiving the filtered digital signal (w[n]) and having a first output (25) connected to the digital loop filter (Loop F), the PWM conversion module being adapted for processing the filtered digital signal (w[n]) and providing at said first output (25) the feedback signal (fb[n]).

Abstract: Disclosed herein is a passive, voltage mode transmitter assembly and method of operation. The passive, voltage mode transmitter assembly comprises a baseband filter configured to filter a source baseband signal, a harmonics filter, connected to the baseband filter, configured to remove harmonics from the filtered, source baseband signal, a passive, voltage mode mixer, connected to the harmonics filter, configured to up-convert an output of the harmonics filter to a radio signal, and a power amplifier, connected to the passive, voltage mode mixer, configured to amplify the radio signal.

Abstract: The invention proposes a built-in self-testing method of a near field communication device including several functions, comprising testing a first internal communication link between a first function and a second function, by sending, on said first internal communication link, a first command from said first function used as a transmitter to said second function used as a receiver, and by checking said first command has been correctly executed by said second function.

Abstract: A method, apparatus, receiver, computer program and storage medium for joint detection are disclosed. The joint detection method includes categorizing interference signals based on level of interference so as to obtain a strong interference signal, cancelling the strong interference signal from a received signal, and performing a joint detection by utilizing a matched filtering result of a remaining signal.

Abstract: A receiver receives a desired radio sub-channel transmitted with an unwanted radio sub-channel by producing signal branches from a received radio signal by treating orthogonal components of the received signal separately and also by using one or both of oversampling and multiple receive antennas. Channel estimates for both the desired and unwanted radio sub-channels are produced for signal branches. The unwanted radio sub-channel bits are estimated from a non-stacked form of the received radio signal. The channel estimates and the estimate of the unwanted radio sub-channel bits are used to reconstruct unwanted radio sub-channel components separately for signal branches. Desired radio sub-channel signal branches are produced by subtracting a corresponding one of the reconstructed unwanted radio sub-channel components from signal branches. A non-stacked desired signal is produced by combining the desired radio sub-channel signal branches.

Abstract: A Reference Signal Received Power (RSRP) value is produced from a received Orthogonal Frequency Division Multiplexed (OFDM) signal that comprises a plurality of reference symbols located at known sub-carrier frequencies and times within the received OFDM signal. RSRP value production involves, for each hypothesized error state selected from a plurality of different hypothesized error states, ascertaining a corresponding hypothesized RSRP value, and then using the hypothesized RSRP values as a basis for determining a value for use as the produced RSRP value (e.g., by selecting a maximum one of the hypothesized RSRP values as the produced RSRP value). In this technology, each of the hypothesized error states is a hypothesized frequency error paired with a hypothesized timing error and the corresponding hypothesized RSRP value is produced by adjusting one or more measured channel estimates as a function of the hypothesized error state.

Abstract: A delta-sigma analog-to-digital converter includes: a summing stage having a first input for an input signal and a second input for a feedback signal; an integrator coupled to an output of the summing stage; an analog-to-digital conversion stage coupled to an output of the integrator; and a switchable gain stage coupled in a feedback path between an output of the analog-to-digital conversion stage and the second input of the summing stage. The switchable gain stage is arranged to switch, responsive to a gain selection signal, between a first gain and a second gain via a transition period comprising time periods during which the switchable gain stage has the first gain interleaved with time periods during which the switchable gain stage has the second gain.

Abstract: A multi-standard transceiver comprises a common balun, a controller, at least one first switch, and at least one second switch. The common balun comprises a primary coil and a secondary coil. The at least one first switch connects the primary coil of the balun to a first signal path associated with a first communication standard, or to a second signal path associated with a second communication standard responsive to a control signal provided by the controller. The at least one second switch connects the secondary coil of the balun to a first amplification path associated with the first communication standard, or to a second amplification path associated with the second communication standard responsive to a control signal provided by the controller. A common mixer is configured to provide upconverted signals to one of the signal paths depending on which communication standard has been selected.

Abstract: A multi-level sigma-delta Analog to Digital converter provides multi-level outputs using a quantizer with reduced quantization levels. The converter comprises a direct path comprising a computation block, an analog integrator and the quantizer with reduced quantization levels. Further, the converter comprises a feedback path arranged to provide to the computation block a feedback analog signal. The direct path comprises a first amplification block having a gain factor which is the inverse of the gain factor of a second amplification block of the feedback path. The converter allows reduction of the complexity of the quantizer.

Abstract: A Process for achieving slot synchronization of the P-SCH sequence in a UMTS communication system, involving the step of receiving (41) said signal including a synchronization sequence (P-SCH); performing a correlation (42) of each received sample with a known synchronization sequence (P-SCH) in order to generate a correlation profile; determining (43) the level of noise and computing a first threshold; suppressing (44) any peaks within said correlation profile having a magnitude inferior to said first threshold; detecting (45) the persistent local maximum peaks over a period of N slots; applying a predetermined mask positioned with respect to said persistent peaks and associated to at least one second threshold value distinctive from said first threshold.

Abstract: A scheme determines the first significant path (FSP) of a received multipath signal, from data defining the relative delay and the amplitude of the individual signal paths occurring in a series of time frames. The scheme includes filtering the data to spread the signal paths, performing a persistence test between frames to reject spurious signal paths, combining the energy of the signal paths in a frame, applying a test to determine the time at which the combined energy satisfies a criterion, and selecting the FSP dependent on that time. The combined energy may be evaluated within a sliding window, and the position of the window within the frame determined that maximizes the combined energy. Alternatively, the combined energy may be evaluated as the cumulative energy through the frame, and the position determined at which the cumulative energy reaches a threshold.