Abstract: The present invention provides a method for power control, a user equipment, a computer program and a storage medium. Based on an adjustment trend of the UE with respect to signal transmission power of a base station and a variation trend of the received signal quality, a current power control mode of the UE is determined, and then a target value of the received signal quality of inner-loop power control is reset after the power control mode of the UE tends to normal, so as to return the transmission power of the base station to the UE to a normal level as soon as possible, thereby to inhibit adverse influences caused by the windup effect.

Abstract: An interface circuit for a switch array having an array of switches, each closeable to couple a row conductor of a plurality of row conductors to a column conductor of one or more column conductors, comprises a current generator and a current detector. The current generator has a plurality of row interface ports for coupling to different ones of the row conductors and is arranged to generate a switch array current for coupling to the row interface ports, the switch array current having a different one of a plurality of different switch array current magnitudes for different ones of the row interface ports, and generate one or more reference currents each having a different reference current magnitude.

Abstract: A protection circuit protects a receiver from high-energy signals. In one exemplary embodiment, the protection circuit comprises a snapback transistor and a controller. The snapback transistor comprises a gate, a drain connected to an input of the receiver and a source connected to ground. The controller configured to connect the gate to a bias voltage to close the gate in a transmit mode, and to disconnect the gate from the bias voltage to open the gate in a receive mode. The snapback transistor is configured to enter into snapback responsive to a high energy signal at the drain to provide a current path from the drain to the source even when the gate is open and thus protect the receiver.

Abstract: A Reference Signal Received Power (RSRP) value is produced from a received Orthogonal Frequency Division Multiplexed (OFDM) signal that comprises a plurality of reference symbols located at known sub-carrier frequencies and times within the received OFDM signal. RSRP value production involves, for each hypothesized error state selected from a plurality of different hypothesized error states, ascertaining a corresponding hypothesized RSRP value, and then using the hypothesized RSRP values as a basis for determining a value for use as the produced RSRP value (e.g., by selecting a maximum one of the hypothesized RSRP values as the produced RSRP value). In this technology, each of the hypothesized error states is a hypothesized frequency error paired with a hypothesized timing error and the corresponding hypothesized RSRP value is produced by adjusting one or more measured channel estimates as a function of the hypothesized error state.

Abstract: There is described a method for compensating the phase and gain distortions of a transmitter analog front end affected by a leakage of a local oscillator. The method comprises generating a single complex tone signal in a digital front end, wherein the generation comprises compensating the signal gain and phase with gain and phase offsets. The method comprises feeding the compensated signal into the transmitter analog front end. The method comprises feeding a corresponding output signal of the transmitter analog front end into a nonlinear component, thereby generating an inter-modulation between the complex tone signal and at least one tone signal due to the local oscillator leakage. The method comprises feeding the output of the nonlinear component into a measurement receiver analog front end.

Abstract: An electronic device as taught herein offers reduced on-chip memory processing of graphics data, while also offering low memory bandwidth requirements. The electronic device includes a host block with off-chip memory, a graphics processing block with on-chip memory, a display controller, and a graphics display. The off-chip memory stores a frame of graphics data. The graphics processing block processes that frame of graphics data in blocks, or “tiles,” of graphics data. For each tile, the graphics processing block fetches rendering instructions and graphics data corresponding to that tile from the off-chip memory, stores the graphics data in the on-chip memory, and renders pixel values for the tile by processing the graphics data in accordance with the rendering instructions. The graphics processing block then sends the rendered pixel values for the tile directly to the display controller and partially updates the graphics display memory with those rendered pixel values.

Abstract: A method of driving a power stage configured to provide both positive output voltage higher than a first potential to a positive output and negative output voltage to a negative output, the method comprising:—generating a first control signal;—generating a second control signal;—operating, the first control signal so as to initiate a charging phase, such that a first duty cycle of the first control signal is controlling an amount of energy to be accumulated;—operating, simultaneously, at the control signals so as to initiate an independent discharging phase of the accumulated energy, in a boost-type to the positive output or in a buck-type or boost-type to the negative output, such that a second and third duty cycles of the second an third control signals are controlling an amount of energy to be discharged.

Abstract: A process for performing Near Field Communication (NFC) between a first NFC device and a second NFC device is provided. The first NFC device includes an NFC transceiver and an FM receiver which are both integrated into the same chip. The provided process involves initializing the first NFC device to perform a device detection polling loop for detecting a second NFC device. The device detection polling loop has activity detection periods, which occur periodically. The first NFC transceiver may then perform a slicing procedure, which slices the activity detection periods into small time slots. Each time slot has a duration smaller than a predetermined value so as to reduce the noise generated by harmonics of the NFC operation frequency which might be audible to the user.

Abstract: A system on chip and associated method facilitates transfer of data between two or more master blocks through a bus on chip. The system creates a direct path for data transferring from a master port of a bus to another master port of the same bus. The bus includes a plurality of signals used to transfer data, address or control information between two or several blocks on chip. The behavior of bus connector block is controlled according to the destination of data coming from a master port. The system includes a master-connector-slave arrangement that enables the direct data communication between two or several master blocks, without taking any slave blocks as the data buffer. A bus connector block is configured to manage bus arbitrating and address decoding, and particularly to create the direct data path between master blocks.

Abstract: Interference detection involves detecting the interference component in the received signal if there is such a component, controlling a band reject filter according to the detected interference component to filter the received signal to suppress the interference component, and synchronizing the receiver to the received signal, wherein the step of detecting the interference component is started before synchronization is achieved. By starting the interference detection without waiting for synchronization to be achieved, rather than following the synchronization, then the interference detection is no longer dependent on the synchronization being achieved.

Abstract: A detection process for a receiver of a wireless communication system based on Multiple-Input Multiple-Output antennas (nT, nR), said receiver processing observations symbols y derived from symbols x transmitted by an emitter through a channel H; characterized in that it involves: —a preprocessing which only depends on the channel H, said preprocessing involving: —a first QRD decomposition (61) for the purpose of decomposing said channel H into two Qext and Rext matrices, with QextHQext=/and Rext being upper triangular; —a lattice reduction (62) for the purpose of generating Qext, Rext and a transformation matrix T; —a second QRD decomposition (63) applied on the matrix Rext T?1 for the purpose of generating two matrixes Q?ext and R?ext, —a loading phase (64, 65, 66) comprising a linear detection process of the observations y for the purpose of generating a value xcenter; —a neighborhood search (67-70) performed in the Original Domain Neighborhood (ODN) with a search center being equal to the result xcenter o

Abstract: A Multi Subscriber Identity Module (SIM) modem capable of receiving paging messages related to at least two subscriber identities comprises a paging configuration block configured to determine whether a collision between paging occasions related to the respective subscriber identities will be systematic or not, and to launch, when the collision has been determined to be systematic, a reselection of a new cell for at least one of the at least two subscriber identities.

Abstract: There is described a method for facial features detection in a picture frame containing a skin tone area, comprising dividing (12) the skin tone area into a number of parts; and for each part of the skin tone area, constructing (14) a luminance map, constructing an edge map by extracting (18) edges from the luminance map, defining (20) an edge magnitude threshold, building (22) a binary map from the edge map by keeping only the edges having a magnitude beyond the defined edge magnitude threshold and eliminating the others; and then extracting (24) facial features from the built binary map. An inter-related facial features detector is further described.

Abstract: A continuous-time MASH sigma-delta analogue-to-digital converter ADC. The ADC may include first and second modulators and an output stage. The ADC may be provided with a first modulator with 1.5 bit and a second modulator with 1 bit each receiving also the feedback from the other modulator. Sampling is at higher rate at the second modulator and decimation is performed before summing its output to the output of the first modulator.

Abstract: The invention relates to a two-stage operational amplifier (400) in class AB for driving a load (RLB, RLA) comprising: an input stage (401) comprising differential input terminals (IN, 1P) and a first differential output terminal (O1P) and a second differential output terminal (O1N) for providing a first differential driving signal (Out1P) and a second differential driving signal (Out1N), respectively; an output stage (402) comprising a first output branch (403) having a first differential input terminal (I1P) operatively connected to the first differential output terminal (O1P) of the input stage (401) to receive the first differential driving signal (OUT1P) and a second output branch (404) having a second differential input terminal (I1N) operatively connected to the second differential output terminal (O1N) of the output stage (401) to receive the second differential driving signal (Out1N), —a control circuit (405) configured to control the output stage (402).

Abstract: A method permitting a UE receiver to detect and then report to the network a scrambling code collision i.e. 2 neighbor cells are transmitting with the same scrambling code while timing is aligned. Furthermore the UE receiver is configured to decode code the PCCPCH's physical channel with all the associated broadcast information in presence of a scrambling code collision at the UE. It also allows the UE to report SFN-SFN information to the network, which is necessary to insure the UE mobility and then prepare the handover to a new detected cell. The process and apparatus described is applicable in the presence of MIMO and further improves the detection of the scrambling code collision in the presence of MIMO.

Abstract: A multi-mode, dynamic, DC-DC converter supplies a dynamically varying voltage, as required, from a battery to an RF power amplifier (PA). In envelope tracking mode, a fast DC-DC converter generates a dynamic voltage that varies based on the amplitude envelope of an RF signal, and regulates the voltage at the PA. A slow DC-DC converter generates a steady voltage and regulates the voltage across a link capacitor. The fast and slow converters are in parallel from the view of the PA, and the link capacitor is between the fast converter and the PA. Because different nodes are regulated, no current sharing is possible between the converters. The link capacitor boosts the dynamic voltage level, allowing a maximum dynamic voltage at the load to exceed the battery voltage. In power level tracking mode, the fast converter is disabled and the link capacitor is configured to be in parallel with the load.

Abstract: A method of protecting digital data stored in a storage medium. The method comprises providing a first and a second addressable storage region in the storage medium, and selector means for selectively indicating one of the first and the second addressable storage regions as active; storing the digital data in the first addressable storage region of the storage medium, wherein the digital data stored in the first addressable storage region is stored encrypted with a first encryption key; and causing the selector means to indicate the first addressable storage region as being active; and, responsive to a trigger event, copying the digital data from the first to the second addressable storage region, wherein the digital data stored in the second addressable storage region is stored encrypted with a second encryption key; and causing the selector means to indicate the second addressable storage region as being active.

Abstract: Electronic device comprising audio/video functionalities including: —a central processing unit (100) comprising means of storage of audio/video files; —a Bluetooth communication controller (200) allowing the wireless communication of audio/video files towards a satellite (20), said communication controller comprising a buffer (210) ensuring the provisional storage of audio/video data received by the central processing unit; characterized in that it comprises —means for transmitting a packets burst of audio/video data towards said communication controller; —means for ensuring an intermittent deactivation of said central processing unit between two bursts of audio packets in order to reduce the electricity consumption of said central processing unit.

Abstract: Amplifier (6) for a wireless receiver, the amplifier comprising a voltage amplifier module having a voltage gain switchable between a first voltage gain value and a second voltage gain value higher than the first gain value, and a resistance module having a resistance switchable between a first resistance value and a second resistance value higher than the first resistance value, an output of the voltage amplifier module being connected to an input of the resistance module, the amplifier further comprising a set of switches configured to set the voltage gain value and the resistance value, the amplifier being operable in:—a nominal mode of operation in which the voltage gain value is set to the second voltage gain value, the resistance value being set to the second resistance value, and—a high linearity mode of operation in which the voltage gain value is set to the first voltage gain value to improve linearity of the amplifier, the resistance value being set to the first resistance value to have the same rat