Abstract: A method and system for high gain auto-zeroing arrangement for electronic circuits. An auto-zero electronic circuit eliminates an offset associated with a test electronic circuit. The test electronic circuit includes a pair of input terminals configured to receive an input voltage signal and a pair of output terminals. The auto-zero electronic circuit includes a pair of source followers, and a pair of capacitors coupled to the output terminals of the test electronic circuit for sampling the offset associated with the test electronic circuit. The auto-zero electronic circuit also includes a differential pair coupled to the pair of source followers. A pair of diode-connected transistors, coupled to the differential pair, is configured to generate biasing voltage signals. The biasing voltage signals modulate the control terminals of a pair of input source followers of the test electronic circuit and eliminate the offset associated with the test electronic circuit.

Abstract: Embodiments of the present disclosure provide a method and system for indicating an attachment and removal for a portable device. The method includes the steps of attaching the portable device to a charging system, delivering current to the portable device from the charging system, the delivered current is limited based on the portable device, replicating the current flowing through the first switch at a second switch, generating a voltage based on the current flowing through the second switch, comparing the voltage with a pre-defined threshold voltage, and indicating at least one of attachment or removal for the portable device based on the comparison.

Abstract: A control method for a sensor-less, brushless, three-phase DC motor. A pulse-width modulation (PWM) duty cycle may be calculated. A voltage induced by rotation of a rotor may be sampled at a first expected zero crossing value to produce a first sampled voltage value. An average of a plurality of sampled voltage values, including voltage values sampled at a plurality of prior expected zero crossing values and the first sampled voltage value, may be calculated. The first sampled voltage value may be subtracted from the calculated average to produce a delta zero crossing error (ZCE). The current value of an integral term corresponding to a rotational period may be updated according to the sign of the ZCE. The integral term may be updated periodically and multiple times during each rotational period. The ZCE may be subtracted from the integral term, and the resulting value may be used to generate one or more time values.

Abstract: A method and system for optimizing the behavior of a charger connected to a portable device when the portable device current exceeds the charger current limit. The system includes a configuration module configured to set a maximum current limit and a register-based current limit values. The system further includes a port power switch configured to limit the portable device current, in the event that the portable device current exceeds the maximum current limit value. The port power switch is configures to modify the portable device current to a predetermined constant current value or reset the current to zero based on the relation between the maximum current limit and the register-based current limit value.

Abstract: The invention is related to a method and system for temperature regulation of a power switch during charging of a portable device. The method includes the steps of establishing a connection between the portable device and a charging circuit, monitoring a charging current supplied from the charging circuit to the portable device, monitoring a temperature of the power switch, while the portable device is being charged, comparing the monitored temperature with a predefined threshold temperature, and restricting the charging current, based on the comparison.

Abstract: A system and method are presented for aligning a rotor in a motor. The motor may include the rotor and a plurality of pairs of electromagnets. One or more pairs of electromagnets may be excited at a first excitation level. The one or more pairs of electromagnets may be less than all of the plurality of pairs of electromagnets. The excitation of the one or more pairs of electromagnets may be increased to a second excitation level over a first period of time. The excitation of the one or more pairs of electromagnets may be decreased to a third excitation level over a second period of time. Exciting the one or more pairs of electromagnets, increasing the excitation, and decreasing the excitation may cause the rotor to stop in a known position.

Abstract: A control method for a brushless, three-phase DC motor. A voltage induced by rotation of a rotor may be sampled at a first expected zero crossing value to produce a first sampled voltage value. An average of a plurality of sampled voltage values, including voltage values sampled at a plurality of prior expected zero crossing values and the first sampled voltage value, may be calculated. The first sampled voltage value may be subtracted from the calculated average to produce a delta zero crossing error. A pulse-width modulation duty cycle may be adjusted based on the delta zero crossing error. The pulse-width modulation duty cycle may be used to control a rotational velocity of the rotor.

Abstract: A system to control access to a nonvolatile memory. The system includes an embedded controller, and a nonvolatile memory including a password. The embedded controller and the nonvolatile memory may be in communication with one another. The system further includes a lock register receiving and storing the password from the nonvolatile memory, and a key register receiving a key from the embedded controller and holding the key for one machine cycle. Further, the system includes a comparator connected between the lock register and the key register. The comparator compares the password received from the lock register and the key received from the key register. Output from the comparator is provided to an access filter connected between the embedded controller and the nonvolatile memory. Based on the comparator output, the access filter may grant or block access to the nonvolatile memory.

Abstract: A simple data transfer mechanism may be combined with static state bus signaling to replace a USB with a digital serial interconnect bus (DSIB). This may eliminate various pull-up/pull-down resistors required in USB, and enable the DSIB to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The DSIB may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The DSIB may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features.

Abstract: An emulation system for charging any arbitrary portable device through a communication port on the portable device. The system includes a receptacle port for communicating with the portable device and a profile database for storing multiple charging profiles. Each charging profile including a set of parameters and at least one exit condition. Further, an emulation module applies a first charging profile to the portable device and monitors the set of parameters associated with the charging profile to identify an associated exit condition. Upon a determination that the exit condition for the first charging profile is met, the emulation module applies a next charging profile to the portable device.

Abstract: A charging method and system for rationing charge or energy supplied by a host to a portable device. The system includes a power switch, and a current sensing module connected to the power switch. The current sensing module detects instantaneous current drawn by the portable device. The system further includes a current register connected to the current sensing module for storing the instantaneous current value. A timing module generates timing information. The system also includes a charge register storing a cumulative charge drawn by the portable device. The cumulative charge is obtained by multiplying the instantaneous current value with the timing information. A threshold database stores a threshold value, and a rationing module connected to the host and the charge register continuously compares the cumulative charge value with the threshold charge value. When the cumulative charge value exceeds the threshold charge value, a control signal is generated.

Abstract: A method and system for detecting a charging current supplied to a portable device through a USB charger. The method includes the steps of connecting a charging circuit to a portable device, allowing the portable device to draw charging current from the charging circuit, measuring the current drawn from the charging circuit, comparing the measured current with a threshold value, making one or more system level decisions regarding charging of the portable device if the detected charging current is below the threshold current.

Abstract: A power controller for a peripheral bus interface. A peripheral bus power controller includes a first terminal, a second terminal coupled to receive an power enable input signal from a host controller, and a third terminal coupled to provide an over-current output signal indicative of an over-current condition to the host controller. The peripheral bus power controller further includes an enable circuit configured to assert a power enable output signal on the first terminal responsive to receiving the power enable input signal and a first buffer configured to provide the over-current output signal to the host controller responsive to the power controller detecting the over-current condition on the first terminal.

Abstract: A switched-capacitor circuit on a semiconductor device may include accurately matched, high-density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining.

Abstract: A switched-capacitor circuit on a semiconductor device may include accurately matched, high-density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining.

Abstract: A switched-capacitor circuit on a semiconductor device may include accurately matched, high-density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch.

Abstract: In one embodiment, an audio-visual content delivery system, such as a set-top box/personal video recorder system, is configured to interface with a local area network (LAN). A packet processing circuit comprised in the system may be configured to filter and route Ethernet packet data received from the LAN to specific ports and/or queues without host processor intervention. The packet processing circuit may utilize a set of filter and routing mechanisms configurable in hardware to interpret various Internet Engineering Task Force (IETF) networking transport protocols, and may transfer the packet data in a format recognized by a variety of consumer subsystems, each of which may be coupled to the decoder.

Abstract: A control circuit for controlling the rotational speed of a fan may include a memory element to store operating data corresponding to an operational profile of the fan defined by RPM (revolutions per minute) versus temperature, with the operating data comprising a respective temperature value and a respective RPM value for each respective operating point representing a change in slope of a function that corresponds to the operational profile of the fan. A processing unit may operate to receive a present temperature value, retrieve the operating data from the storage unit, and identify a pair of consecutive operating points such that the present temperature value is greater than a lower respective temperature value of the pair of consecutive operating points, and lower than a higher respective temperature value of the pair of consecutive operating points.

Abstract: A system including a serialized secondary bus architecture. The system may include an LPC bus, an I/O controller, a serialized secondary bus, and at least one slave device. The LPC bus may be connected to the I/O controller, and the at least one slave device may be connected to the I/O controller via the serialized secondary bus. The serialized secondary bus has a reduced pin count relative to the LPC bus. The I/O controller may receive bus transactions from the LPC bus. The I/O controller may translate and forward LPC bus transactions to the at least one device over the secondary bus. The I/O controller may include a processing unit. The processing unit may initiate bus transactions intended for the at least one slave device. The I/O controller may also include a bus arbitration unit. The bus arbitration unit may arbitrate ownership of the secondary bus between the processing unit and the LPC bus.

Abstract: System and method for digitizing analog voltage signals. A first voltage signal may be received at a comparator. A ramp signal may be received at the comparator. The ramp signal may be generated by a ramp generator. An output signal may be generated by the comparator. The output signal may indicate whether the analog voltage signal or the ramp signal is greater. The output signal may be conveyed to logic circuitry by the comparator. Control information may be conveyed by the logic circuitry to the ramp generator. The ramp generator may generate the ramp signal based on the control information. The logic circuitry may determine a digital representation of the first voltage signal based on the output signal from the comparator and the control information.