Abstract: A system including a serialized secondary bus architecture. The system may include an LPC bus, an I/O controller, a serialized secondary bus, and at least one slave device. The LPC bus may be connected to the I/O controller, and the at least one slave device may be connected to the I/O controller via the serialized secondary bus. The serialized secondary bus has a reduced pin count relative to the LPC bus. The I/O controller may receive bus transactions from the LPC bus. The I/O controller may translate and forward LPC bus transactions to the at least one device over the secondary bus. The I/O controller may include a processing unit. The processing unit may initiate bus transactions intended for the at least one slave device. The I/O controller may also include a bus arbitration unit. The bus arbitration unit may arbitrate ownership of the secondary bus between the processing unit and the LPC bus.

Abstract: A system for measuring a voltage drop between two nodes in an electrical circuit, comprising a switched capacitor integrator (SCI), a comparator and a counter. The SCI alternately (a) captures charge onto a set of sampling capacitors and (b) selectively accumulates/transfers the charge onto a pair of integration capacitors, where the charge includes a first portion that is based on the voltage drop and a second portion that depends on a digital indicator signal. The comparator generates the digital indicator signal based on whether an analog output of the SCI is positive or negative. The counter counts a number of ones occurring in the digital indicator signal during a measurement interval. At the end of the measurement interval, the count value represents a measure of the voltage drop. Knowing the resistance between the two nodes, the voltage drop may be converted into a current measurement.

Abstract: The present disclosure describes a system and method for implementing bus operations with precise timing. The system includes a trigger descriptor register for a bus operation. The trigger descriptor register includes a bus definition field, which further includes data and address fields for providing data and address information for the bus operation. The trigger descriptor register may also include a holdoff time field to store a time value and includes an event select field to select a trigger for the bus operation. A processor configures the trigger descriptor register. A counter may count based on a time period such that at the end of the counting, the bus operation is performed based on the data and address fields. The time period is derived from one or more of the holdoff field or an external timer. The disclosed method and system employ hardware assist for maintaining precise timing while performing bus operations.

Abstract: An emulation system for determining an arbitrary charging protocol in USB charging ports and for optimally charging portable devices. The emulation system comprises a power switch for powering on the emulation system, a high-speed data switch for transferring data to and from the portable device, a USB receptacle port including data pins (DP and DM), VBUS, and GND. The emulation system further comprises a profile database that stores one or more charging profiles including one or more stimulus-response pairs for each charging profile. The emulation circuit further includes emulation circuitry for detecting stimulus generated by the portable device and for generating responses according to the charging profiles.

Abstract: A circuit may comprise an amplifier powered by a first supply voltage, with a first input of the amplifier coupled to a stable reference voltage, and the output voltage of the amplifier provided as a designated supply voltage to an oscillator configured to produce a periodic signal having a specified frequency. The circuit may further include a control circuit coupled to a second input of the amplifier, to the output of the amplifier, and to ground, and configured to control the rate of change of the output voltage of the amplifier with respect to temperature. This rate of change may be specified according to a characterization of the oscillator over supply voltage and temperature, and may result in stabilizing the specified frequency across temperature. The periodic signal may therefore be unaffected by variations in the first supply voltage, and the amplitude of the periodic signal may be proportional to the stable reference voltage.

Abstract: A memory alignment system for efficient data transfer between a local memory that is configured in a host system, and a remote memory, comprises a data communications controller configured in the host system to align transmitted and received data based on formatting information received from the host system. When transmitting data from local system memory, for example over an Ethernet connection, communications control driver software may first write formatting information corresponding to the data into the data communications controller. The data communications controller is operable to align the data based on the formatting information as the driver software moves the data into a configurable transmit data buffer inside the data communications controller. Similarly, the driver software may write formatting information for receive data into a receive-format configuration buffer.

Abstract: A system may comprise multiple master/slave devices coupled to a common bus, where one of the devices may operate as the current master device and the other devices may operate as current slave devices. Current slave devices may embed bus ownership request information within response packets transmitted in response to standard bus operations, such as reads and writes, issued by the current master device. When the current master device is idle, its bus interface may continually poll the current slave devices at regular intervals, according to a specified protocol, to ascertain whether any of them are requesting bus ownership. A response to a request for bus ownership received by the current master device may be configured according to desired system functionality. In one system, ownership may always be transferred to the requesting device.

Abstract: An integrated circuit may include one or more cells, with each cell comprising a first and a second input terminal, a first and a second output terminal, and a number of connection stages configured to couple each input terminal to a corresponding respective output terminal. The stages may include one stage per metal layer of the integrated circuit and one stage per VIA layer of the integrated circuit. Each stage may be configured with a pair of input ports and a pair of output ports. Each output port of a stage may serially connect to a corresponding respective input port of a first adjacent stage, and each input port of the stage may also serially connect to a corresponding respective output port of a second adjacent stage. The pair of input ports may also be configured to programmably connect to the pair of output ports within the same stage, according to one of two different connection patterns, to establish a respective connection within the stage.

Abstract: A power controller for a peripheral bus interface. A peripheral bus power controller includes a first terminal, a second terminal coupled to receive an power enable input signal from a host controller, and a third terminal coupled to provide an over-current output signal indicative of an over-current condition to the host controller. The peripheral bus power controller further includes an enable circuit configured to assert a power enable output signal on the first terminal responsive to receiving the power enable input signal and a first buffer configured to provide the over-current output signal to the host controller responsive to the power controller detecting the over-current condition on the first terminal.

Abstract: A method and system for transferring data between two slave devices. A system includes a master device and first and second slave devices coupled to the master device by a peripheral bus. The master device is configured to configure the first slave device as a source for a read operation, configure the second slave device as a target for a write operation, provide a clock signal to both the first slave device and the second slave device, and initiate a read operation of the first slave device. Initiation of the read operation causes the first slave device to provide data onto the peripheral bus. Responsive to the master device initiating the read operation, the second slave device receives the data provided on the peripheral bus by the first slave device. The master device is configured to ignore the data provided on the peripheral bus by the first slave device.

Abstract: An input protection circuit (IPC) may prevent an input signal from propagating into a system, such as an integrated circuit (IC), when the voltage level of the input signal exceeds a specified value. The IPC may be configured to compare the input signal voltage, which may be that of an external input signal received by the system, with a reference voltage, which may be the power supply voltage. If the input signal voltage exceeds the reference voltage, the output of the IPC may be set to the value of a specified clamp voltage. If the input signal voltage does not exceed the reference voltage, the output of the IPC may track (or follow) the input signal voltage. For certain integrated circuits, the IPC may be configured to provide circuit protection for an input signal voltage ranging between 0V to 5V, and a power supply voltage ranging between 3.0V and 3.6V.

Abstract: System and method for providing a high speed connection to a memory medium of a mobile device. The mobile device may be a mobile phone or other type of portable electronic device. The memory medium may be removable and/or may be flash memory, as desired. The mobile device may include a USB hub that provides a direct high speed connection between an external device and a memory medium of the mobile device. The USB hub may also provide a connection (possibly high speed) between the external device and the processor of the mobile device. The mobile device may also include a high speed connection between the processor of the mobile device and the memory medium.

Abstract: System and method for determining closure of an electronic device. The electronic device may include a top portion and a bottom portion, and may be connecting via a hinge or other closing mechanism. The top portion and/or the bottom portion may include one or more capacitive sensors which provide signals corresponding to physical contact and a controller coupled to the one or more capacitive sensors. The controller may operate to receive the signals from the one or more capacitive sensors, determine if the electronic device has been closed based on the received signals, and initiate a sequence of events corresponding to the closure of the electronic device. The sequence of events may result in the device entering a low power state.

Abstract: Low cost fingerprint system having a single chip solution includes a circuit board, a fingerprint sensor array fabricated onto a first surface of the circuit board, and an integrated circuit die for processing information received from the fingerprint sensor array is mounted directly to a second surface of the circuit board. The integrated circuit die may be electrically connected to the sensor by, for example, vias in the circuit board.

Abstract: A method for transferring data between a host device and an external device is described. The external device has FAT32 file system. The method accepts parameters for an incoming data file from the host device. Further, the method allocates memory blocks for the incoming file data on the external device based on the parameters and indexes the allocated memory blocks on a memory index table to create a file footprint. The method reads the memory index table to identify the file footprint and receives the incoming file data from the host device.

Abstract: A low-current differential signal activity detector circuit may be configured to reject large common mode signals on differential input lines, while still detecting smaller differential signals applied to the same set of differential input lines. The detector circuit may comprise a translinear buffer that is driven at the buffer input and at the buffer output by the differential input signals. The differential signal thereby driving the inputs of the detector circuit may be half-wave rectified through the buffer output devices and may be filtered to provide the detected output. When applying a common mode signal, the buffer's input and output may track each other, and no current may be rectified in the output devices, thus providing common-mode signal rejection. The detector circuit may also be configured with two buffers having their outputs coupled to a common node, each buffer input driven by a respective one of the differential input signals.

Abstract: A system for high-speed data transfer within a portable device, such as, cell phone or a set-top box, which includes a memory medium and a processor. The system includes a first port for coupling to the processor, and a second port for coupling to the memory medium. Further, the system includes an embedded Universal Serial Bus (USB) host configured for receiving data transfer commands from the processor, and transferring data at high speed between a USB device on the processor and the memory medium. Moreover, a data path is provided between the embedded USB host and the first port.

Abstract: Hub apparatus that supports multiple high speed devices and a super speed device. The hub apparatus may include at least one upstream port for coupling to a host device and at least one downstream port for coupling to at least one downstream device. The hub apparatus may further include an embedded device as well as an internal hub coupled to the upstream port, the embedded device, and the at least one downstream port. The internal hub may be configured to provide a connection between the host device and the embedded device at a first speed (e.g., USB high speed). However, when supported by the host device, the embedded device may communicate with the host device at a higher speed than the first speed (e.g., USB super speed), e.g., without using the internal hub.

Abstract: Reporting a faulty charging device. A mobile device may determine if a charging device is a faulty charging device. The determination may be performed after coupling the charging device to a power source and to the mobile device. If the charging device is a faulty charging device, the mobile device may report a location of the faulty charging device over a network.

Abstract: A method and system for securing access to a storage device including one or more locked logical sections. The method includes providing an interface device including a first port connected to a computing system and a second port connected to the storage device. Further, the method includes receiving a unique identifier from a wireless device, and deriving a key from the unique identifier. Based on the derived key, the method unlocks a logical section in the storage device. The method may further store access permission rights for the locked logical sections in the interface device and unlock the logical section based on the access permission rights. Moreover, the method may further authenticate the identity of a user of the wireless device for unlocking the storage device.