Abstract: A communication system, network, interface, and port architecture are provided for transporting different types of data across a network. The network can be arranged by connecting the ports in a daisy chain fashion to achieve a ring architecture or topology. The network forwards data according to a specific network protocol, and any incoming data that follows that protocol will be sent onto the network. If the incoming data protocol does not match the network protocol, then the incoming data is not sent immediately to the network, but instead is sent to an input pin of a device upon the network specifically designed to receive that incoming data. The network, therefore, has ports that support both compliant and non-compliant incoming data, and the devices that produce such data.

Abstract: A system and method for monitoring usage of peripheral devices and placing a second peripheral device in a low power state when the usage indicates that a second peripheral device is not being used. For example, if a computer system detects that a user's current typing rate indicates the user probably has both hands on a keyboard, the computer system may generate a signal to the computer mouse to enter a low power state. The computer system may use prior usage for a user to determine when current usage indicates that the second peripheral device is not being used. After the second peripheral device is placed in a low power state, the computer system may generate a signal to the second peripheral device to return to a normal power state when the computer system determines that the user no longer has both hands occupied.

Abstract: A duty cycle comparator is described for comparing the duty cycles of two digital signals. The duty cycle comparator comprises a first controllable current source, a second controllable current source and a charge accumulation device. The comparator provides an output signal that is representative of the difference between the duty cycles independent of the frequency of the two digital signals.

Abstract: A communication system, clock generation circuit, and method are provided for receiving jitter upon data and to generate a clock reference that does not contain the received jitter. The clock reference can be used either by a digital subsystem of a communication system node, or can be transmitted as substantially jitter-free data from that node to a downstream node of the communication system. Instead of recovering the clock reference from the data having jitter, a pattern is regularly defined within the data stream preferably at periodic, timed intervals. The data pattern may be made up of a series of non-transitions which, regardless of any jitter in the data itself, does not impute any jitter onto a phase-locked loop triggered from an edge of the non-transitioning data pattern. Using the edge as a reference point, a jitter-free clocking signal can be derived at the same frequency as a clocking signal which would normally be produced from the jitter-induced data.

Abstract: A regulator circuit may be configured to operate with multiple power supplies. The regulator circuit may be configured to receive an input voltage and provide a regulated output voltage at an output terminal as a function of the input voltage. The regulator may include at least two drivers. A first driver may have a driver output coupled to the output terminal and have a supply terminal coupled to a high power supply, and a second driver may have a driver output coupled to the output terminal and have a supply terminal coupled to a low power supply. A selector circuit may be configured to compare the input voltage with a control voltage that has a magnitude just below a magnitude of the low power supply, to determine which driver to select from the first driver and the second driver, and enable either the first driver output or the second driver output to be active according to which driver has been selected.

Abstract: A communication system for transmitting and receiving a sequence of bits, and the methodology for transferring that sequence of bits are provided. The communication system includes a transmitting circuit and a receiving circuit. Within the transmitting circuit is a scrambler that comprises a shift register, an enable circuit, and an output circuit. The shift register temporarily stores n bits within the sequence of bits, and the enable circuit enables the shift register to store bits that arise only within the payload section of a frame. The output circuit includes a feedback, and several taps within the n stages to scramble logic values within the sequence of n bits output from the shift registers thus effectively preventing in most instances the sequence of bits from exceeding n number of the same logic value. Within the receiving circuit is a descrambler also having a shift register, an enable circuit, and an output circuit. The descrambler recompiles the scrambled data back to its original form.

Abstract: System and method for enumerating and/or enumerating a device. The device may be a USB portable device which adheres to a first standard, e.g., the USB specification, and may engage in enumeration with respect to a USB hub/USB host device. Where a battery included in the device is sufficiently low, the device may engage in low power enumeration, e.g., to begin charging the device using enumerated power. Low power enumeration may allow the device to enumerate even when the device is incapable of powering on. Additionally, or alternatively, the device may determine whether the hub/host device is capable of providing high power charging. If it is, the device may begin charging the battery of the device using power provided by the hub/host device at a high power level.

Abstract: An address assignment mechanism. A computer system may include one or more types of slave devices. Each slave device includes an internal device ID. Slave devices of the same type include the same internal device ID. The master device may broadcast a message through the use of a protocol to each of the slave devices to initiate an address assignment operation. Each of the slave devices determines whether the broadcast device ID included in the broadcast message matches the internal device ID associated with the slave device. If the broadcast device ID matches the internal device ID, the linear bus address included in the broadcast message is assigned to the slave device. The bit size of the linear bus address may be smaller than that of the broadcast device ID. After the address assignment operation, the master device may communicate with the slave device using the assigned linear bus address rather than the device ID.

Abstract: A computer system may receive one or more credentials of a user (e.g., username, password, etc.) from an integrated circuit (IC) device carried by the user. The computer system may include an IC device interface to receive the user credential(s) from the IC device. The IC device interface may be coupled to a CPU of the computer system through a low pin count (LPC) bus. The user credential(s) may be used to grant access to software and/or to grant access to information. Access may be granted to information stored on the computer system. In some embodiments, the computer system may be coupled to a network and transmit the user credential(s) from the IC device and a request for access of information to a service provider coupled to the network. The service provider may grant or deny the request for access of information based on user credential(s).

Abstract: A resistor/capacitor identification detection (RCID) circuit may provide system level identification of hardware (e.g. circuit board ID) through a single pin interface, by identifying up to a specified number of more than two quantized RC time constant states by measuring the discharge and charge times of an external RC circuit coupled to the single pin. The RCID circuit may initiate the discharge followed by a charging of the external RC circuit. The signal developed at the signal pin may be provided to the input of a threshold detector, with the threshold set at a specified percentage of a supply voltage used for operating the RCID circuit. The digitized output of the threshold detector may be used to gate a counter, after having been filtered through an input glitch rejection filter. A resolution of the counter may be determined by a high frequency clock used for clocking the counter. The numeric values of the charge and discharge times may be stored in data registers comprised in the RCID circuit.

Abstract: A USB device may be simultaneously configured and accessed by two or more USB hosts. The USB device may include separate upstream ports and buffers for each host, and a multi-host capable device controller configured to respond to simultaneous USB requests received from more than one host. The USB device may maintain a dedicated address, configuration, and response information for each host. The USB device may include a shared USB function block, and a multi-host controller configured to establish concurrent respective USB connections between the shared USB function block and two or more USB hosts, to allow the two or more USB hosts to simultaneously configure the USB device for the shared USB function. The multi-host controller may be configured to receive and respond to simultaneous respective USB access requests for the shared USB function sent by the two or more USB hosts.

Abstract: An Automatic System Clock Detection System (ASCDS) may provide integrated circuits (ICs) with the capability to detect the frequency of an external crystal oscillator or clock source, and adjust the IC's internal PLL accordingly for proper IC operation. The frequency detection and PLL adjustment may be performed without any additional pins on the IC, and/or without requiring any additional external information. The ASCDS may be configured with an internal ring oscillator, which may be generated from standard logic elements, a watchdog counter, and an input clock counter. When the IC comes out of power on reset (POR), the ASCDS may compare the input clock counter with the watchdog counter, and determine the clock frequency of the input clock. It may then set the PLL parameters to ensure correct IC operation.

Abstract: A solid-state floppy disk drive is disclosed. In one embodiment, a solid-state floppy disk drive may include a non-volatile memory and a connector for coupling the solid-state floppy disk drive to a computer system. The non-volatile memory may store instructions and data which may allow the solid-state floppy disk drive to emulate a mechanical floppy disk drive having a bootable floppy disk inserted into it. The computer system may be booted using the solid-state floppy disk drive.

Abstract: In one set of embodiments, a circuit may be implemented to deliver accurately ratioed currents to a remotely located semiconductor device that has a substantially non-linear input-output characteristic that varies with temperature and is subject to effects of electromagnetic interference (EMI). The circuit may be configured to use common mode rejection by establishing an identical impedance at each of the two terminals of the remotely located semiconductor device, in lieu of coupling shunting capacitor(s) across the terminals, in order to reject EMI signals while performing temperature measurements using the remotely located semiconductor device. This may facilitate maintaining fast sampling times when performing temperature measurements, while providing a more effective method for handling EMI induced currents that may lead to temperature measurement errors, thereby eliminating those errors.

Abstract: System and method for enumerating and/or enumerating a device. The device may be a USB portable device which adheres to a first standard, e.g., the USB specification, and may engage in enumeration with respect to a USB hub/USB host device. Where a battery included in the device is sufficiently low, the device may engage in low power enumeration, e.g., to begin charging the device using enumerated power. Low power enumeration may allow the device to enumerate even when the device is incapable of powering on. Additionally, or alternatively, the device may determine whether the hub/host device is capable of providing high power charging. If it is, the device may begin charging the battery of the device using power provided by the hub/host device at a high power level.

Abstract: A level-shifter circuit configured to transfer data between two voltage supply domains may eliminate crowbar current while simultaneously providing a valid output signal. The level-shifter circuit may transfer a data signal between the two voltage domains using a latch that is capable of maintaining its output level—based on the destination supply rail—to correspond to the same state to which the level of the input signal—based on the originating supply rail—corresponds, even when the originating supply is decreased to a zero-volt state, or to a voltage equivalent to a low state. During normal operation, when both power supplies are available, the signal at the output of the latch, and hence at the output of the level-shifter circuit may toggle to always track the input signal. Thus, the level of the signal at the output of the level-shifter may always represent the same state (e.g.

Abstract: A communication system, clock recovery circuit, and method are provided for allowing data to be transmitted across a communication system and between clock recovery circuits absent a clock master specifically designed for one node of the communication system. Absent a clock master, the communication system is permitted to enter into an all slave mode, with periodic unlock conditions possibly rotating about the communication system ring topology. However, the unlock condition can be readily detected and if the received data bitstream formed into a recovered clock exceeds a threshold above or is less than a threshold below a reference clock generated during instances of unlock, then the clock recovery circuit will fix the synchronizing clock to the reference clock, and cause the bitstream to resynchronize to the reference clock before the reference clock is again disabled to allow the communication system to re-enter the all slave and rotating unlock condition.

Abstract: A voltage regulator may include a resistor-based voltage divider circuit generating a desired output voltage from a supply voltage, an output NMOS device whose source terminal may be configured as the output of the voltage regulator and whose drain terminal may be configured to receive the supply voltage, and a control circuit configured to control the output NMOS device to maintain the desired output voltage at the output of the voltage regulator. The control circuit may be configured to receive the desired output voltage from the voltage divider circuit as a first input, and to receive the output of the voltage regulator fed back as a second input to form a feedback loop.

Abstract: A power supply management device including a current limiting protection circuit. The power supply management device may include an output terminal, a first transistor, a replication circuit, a comparator circuit, and a control circuit. The first transistor may provide an output current to the output terminal of the power supply management device. The replication circuit may be connected to the first transistor and may replicate the output current to a separate path to monitor the output current. The comparator circuit may be connected to the replication circuit and may compare the replicated output current to a current reference. The control circuit may be connected to the first transistor and to the comparator circuit. In response to the replicated output current being greater than the current reference, the control circuit may limit the output current the first transistor provides to the output terminal to an amount corresponding to the current reference.

Abstract: A system, e.g. an integrated circuit or part, may include a plurality of pads, e.g. digital I/O pads, each comprising a physical pad and associated pad circuit. In case of an ESD event affecting one or more of the digital I/O pads, PMOS devices configured in an output buffer section between an I/O pad supply rail and the physical output pad—within their respective pad circuits in the affected digital I/O pads—may all be turned on in response to the ESD event. This may allow the capacitance of each pad, in some cases approximately 3 pF capacitance per pad, to charge up, absorbing the energy of the ESD event and reducing the peak voltage the integrated circuit or part experiences as a result of the ESD event. The reduced peak voltage may be directly correlated with improved ESD performance of the product.