Abstract: An operational amplifier including an input stage. The input stage may include first and second differential input circuits and a first current mirror. When an input terminal of the operational amplifier is at a positive voltage rail, the first differential input circuit may be activated. When the input terminal is at a negative voltage rail, the second differential input circuit may be activated. In either case, this may cause the first current mirror to provide a current of a predetermined value to each of first and second input terminals of a control circuit, and to each of first and second nodes coupled to a rail-to-rail output stage. The input stage may maintain the current provided to each of the input terminals of the control circuit and to each of the nodes coupled to the rail-to-rail output stage constant over the full input voltage range from the negative voltage rail to the positive voltage rail.

Abstract: A shared USB device may be simultaneously configured and accessed by two or more USB hosts by using a multi-host capable device controller. The multi-host capable device may include separate upstream ports and buffers for each host, and may be configured with the capability to respond to USB requests from more than one host. The multi-host capable device may maintain a dedicated address, configuration, and response information for each host. Each host may therefore establish a dedicated USB connection with the sharing device without the sharing device having to be re-configured or re-enumerated each and every time the upstream hosts alternate accessing the USB device.

Abstract: A system and method for protecting register write operations, especially register write operations performed in a USB PHY. A USB transmitter/receiver, operable to receive a register write command from a USB LINK device, may monitor the write sequence initiated by the register write command to determine if/when the register write sequence has been interrupted. In monitoring the register write sequence, the USB transmitter/receiver is operable to discard the register write command if a DIR signal issued by the USB transmitter/receiver is asserted during the register write sequence and/or if an STP signal received by the USB transmitter/receiver is asserted during the register write sequence, where STP may be part of a normal register write operation. The USB transmitter/receiver is further operable to allow the register write sequence to complete if the STP signal and the DIR signal are not asserted during a predetermined period of the register write sequence.

Abstract: A device may include an upstream port and several downstream ports configured to transfer data at a different data transfer rate than the upstream port. The device may also include several downstream data handlers, each coupled to a respective one of the downstream ports, and an upstream data handler coupled to the upstream port. The data handlers are configured to implement a USB protocol. The upstream data handler is configured to provide data received via the upstream port to each of the downstream data handlers. Accordingly, the upstream data handler is shared between the various downstream data handlers.

Abstract: System and method for switching logic in a Universal Serial Bus hub. The USB hub may include upstream logic and downstream logic for sending and receiving information from a host controller and a USB device respectively. The USB hub may include a plurality of ports operable to couple to a plurality of devices, including a first port coupled to the upstream logic and a second port coupled to the downstream logic. The USB hub may also include switching logic operable to switch the upstream and the downstream logic with respect to the first port and the second port respectively. The switching logic may switch the upstream and downstream logic by decoupling the first port from the upstream logic, decoupling the second port from the downstream logic, and coupling the second port to the upstream logic. Additionally, the first port may be coupled to the downstream logic.

Abstract: A three-level detector circuit may comprise an input node and a pair of diode-connected transistors having respective drain terminals coupled to the input node. The pair of diode-connected transistors may be configured to set a voltage if the input voltage at the input node corresponds to an open input. The three-level detector circuit may further comprise a pair of inverting stages coupled to the input node, the pair of inverting stages configured to distinguish between low, high, and/or open inputs. The three-level detector circuit may also comprise a pair of latches, e.g. D-flip-flops, each of the pair of latches having a respective input coupled to a respective output of a respective one of the pair of inverting stages, and each of the pair of latches configured to latch a present state of the input in detection mode. In one set of embodiments, the three-level detector circuit is operable to cease conducting current after the present state of the input has been latched.

Abstract: A system for automatically switching peripheral connectivity between two host devices based on respective connectivity of the hosts. The method may be used where peripherals are usually attached to one host and are automatically switched to a second host when the second host is attached to the system. A USB switching hub may be operable to automatically switch connectivity of the peripheral device(s) from the first host device to the second host device when the second host device is connected to the USB device. This automates the process for the end user when normally all peripherals are attached to one host, and some or all peripherals are shared with a second host when the second host is attached.

Abstract: A linear, half-rate clock and data recovery (CDR) circuit for recovering clock information embedded in a received data signal. The half-rate CDR circuit comprises a phase detector that may receive the data signal and generate a phase error signal representative of the phase difference between the received data signal and a clock signal produced by a voltage-controlled oscillator (VCO) of the CDR circuit. The half-rate CDR typically changes the frequency of the clock signal and generates a clock signal that is aligned with the baud center of the received data signal. More specifically, when the half-rate CDR circuit is in a locked condition, both the rising and falling edges of the clock signal are aligned with the baud center of the received data signal. The half-rate CDR preferably generates a clock signal with an average frequency that is half the data rate of a received data signal.

Abstract: In one set of embodiments, trimming of a reference, which may be a bandgap reference and which is configured on an integrated circuit, may be controlled by an algorithm executed by logic circuitry also configured on the integrated circuit. The bandgap reference may be configured to generate a reference voltage provided to an analog to digital converter (ADC) comprised in a temperature sensor that may also be configured on the integrated circuit. The logic circuitry may be configured to execute one or more of a variety of test algorithms, for example a Successive Approximation Method or remainder processing, that are operable to adjust values of reference trim bits used in trimming the bandgap reference.

Abstract: In various embodiments, a system may include a processor, a host controller coupled to the processor, a Universal Serial Bus (USB) device coupled to the host controller and a non-USB device coupled to the USB device. In some embodiments, the host controller may be configured to communicate with the non-USB device through a small computer system interface (SCSI) pass-through command. In some embodiments, a method may include a host controller sending a SCSI pass-through command to a USB device coupled to a non-USB device, the USB device receiving the SCSI pass-through command, and the USB device interacting with the non-USB device in response to the SCSI pass-through command.

Abstract: A temperature sensor circuit and system providing accurate digital temperature readings using a local or remote temperature diode. In one set of embodiments a change in diode junction voltage (?VBE) proportional to the temperature of the diode is captured and provided to an analog to digital converter (ADC), which may perform required signal conditioning functions on ?VBE, and provide a digital output corresponding to the temperature of the diode. DC components of errors in the measured temperature that may result from EMI noise modulating the junction voltage (VBE) may be minimized through the use of a front-end sample-and-hold circuit coupled between the diode and the ADC, in combination with a shunt capacitor coupled across the diode junction. The sample-and-hold-circuit may sample VBE at a frequency that provides sufficient settling time for each VBE sample, and provide corresponding stable ?VBE samples to the ADC at the ADC operating frequency.

Abstract: A fan controller may be integrated in silicon and may use an embedded microcontroller to implement a digital fan control algorithm. The microcontroller may continually monitor temperature and sample the speed of the controlled fan. The speed of the fan may be compared to RPM values fitted on a desired curve that is representative of the Temperature-versus-RPM function for the controlled fan. The fan control algorithm may be based on a ramp-rate closed-loop controller (RRCC), which may be operated to drive the fan to the desired speed at different rates, depending on the difference between the desired RPM and the actual RPM of the fan. The fan may also provide a Fan ID feedback signal to the microcontroller, which may use the Fan ID feedback signal upon system start-up to initialize the RRCC range settings and select the appropriate Temperature-versus-RPM function curve based on pre-determined values for the given fan.

Abstract: A current-mode direct conversion RF receiver is presented. In one set of embodiments the RF receiver comprises a simple transconductor input stage to create a current-mode modulated signal from a voltage-mode modulated signal. A downconversion mixer may be coupled to the transconductor input stage via a low impedance current cascode stage, and may operate to create a set of current-mode quadrature baseband signals from the current-mode modulated signal. The downconversion mixer may be implemented with a transistor-switching network, which may be driven by a phase locked loop (PLL) with quadrature outputs. The set of current-mode quadrature baseband signals may be converted back to the voltage domain by a transimpedance filter, which may perform channel selection for the receiver. The transimpedance filter may additionally include a low frequency zero to remove DC offsets.

Abstract: A computer system, more generally a master-slave system, may be configured with interrupt handling capability without additional dedicated interrupt lines. An interrupt condition may be bound with its relevant cause information and transmitted by a slave device during a typical response to any operation that a master device may have issued, such as a read or a write. In addition, a link level protocol may be configured in the bus interface of the master device to continually poll specified addresses, or to issue a unique command targeted at interrupts. The master device may be unaware of the unique requests, as the bus may remain idle as seen by the master device. The response to the unique requests may be similar to the interrupt message information transmitted as part of a response to a standard request that may be made by the master device.

Abstract: A control signal value, such as a duty cycle value for a Pulse Width Modulated (PWM) generator output, for controlling and/or powering a fan may be calculated using an autofan function configured with dynamic hysteresis control (DHC). As part of the DHC, the PWM duty cycle value may be determined by applying a hysteresis component at every point of the autofan function relating the PWM duty cycle to temperature. The PWM duty cycle value may be computed based on two functions, each function relating the PWM duty cycle to temperature, the first function applied when the temperature is increasing, and the second function applied when the temperature is decreasing. When a newly computed PWM duty cycle value falls within a range of duty cycle values defined by the hysteresis value, the current duty cycle of the PWM generator output may remain unchanged, minimizing noise resulting from the fan changing speed.

Abstract: A method for implementing a counter in memory, e.g., non-volatile memory such as flash memory. A first number of first binary values indicating a first portion of a current number of the counter in a binary field may be stored in a portion of memory. Storing the first number may also include increasing the number of first binary values in the binary field. Additionally, a second number indicating a second portion of the current number of the counter may be stored in another portion of memory. The second number may specify the number of times the first binary values has comprised the entirety of the binary field. Thus, the first number and second number may specify the current number of the counter. Storing the first and second number may be performed a plurality of times to implement a counting function of the counter.

Abstract: A driver circuit with variable output voltage and current. A source input terminal of the driver circuit may receive a source control signal. A voltage control circuit may drive one of the terminals of a first switch to a source voltage. If the source input terminal receives an asserted source control signal, the first switch is turned on and the voltage control circuit drives an output terminal of the driver circuit to the source voltage. A source current mirror may regulate a source current provided to the output terminal of the driver circuit. A sink input terminal of the driver circuit may receive a sink control signal. If the sink input terminal receives an asserted sink control signal, a second switch is turned on and the output terminal is driven to a sink voltage. A sink current mirror may regulate a sink current provided to output terminal of the driver circuit.

Abstract: An accurate temperature monitoring system that uses a precision current control circuit to apply accurately ratioed currents to a semiconductor device, which may be a bipolar junction transistor (BJT), used for sensing temperature. A change in base-emitter voltage (?VBE) proportional to the temperature of the BJT may be captured and provided to an ADC, which may generate a numeric value corresponding to that temperature. The precision current control circuit may be configured to generate a reference current, capture the base current of the BJT, generate a combined current equivalent to a sum total of the base current and a multiple of the reference current, and provide the combined current to the emitter of the BJT. In response to this combined current, the collector current of the BJT will be equivalent to the multiple of the reference current. The ratios of the various collector currents conducted by the BJT may thus be accurately controlled, leading to more accurate temperature measurements.

Abstract: If a USB device is turned off or is not active, the device may be electrically disconnected from a USB host controller. The device may be electrically disconnected through a physical interface on the device. In some embodiments, if the device becomes active during a wait period (e.g., 2-3 seconds) prior to electrically disconnecting the device, the device may not be electrically disconnected. In some embodiments, when the device is electrically disconnected from the USB host controller and no system activity of a bus mastering peripheral is occurring, the CPU may enter a low power state if other conditions are met. In some embodiments, if the USB device becomes active after electrically disconnecting, the electrical disconnection may be discontinued.

Abstract: A system and method for maintaining communications with a radio frequency (RF) peripheral device such as an RF input device and an RF output device. A computer may search for an RF peripheral device by transmitting a signal request on available channels until a response is received from an RF peripheral device. If the RF channel becomes busy and/or jammed, the RF peripheral device may tune into a predetermined channel while the computer scans for another channel to use. Once the computer finds a better channel, the computer may go to the predetermined channel and broadcast the new channel location to the RF peripheral device. In addition, if an RF signal arrives incomplete or corrupt, the computer may transmit a negative acknowledgement to the RF peripheral device, which may retransmit the previous RF signal.