Patents Assigned to Stats Chippac Ltd.
  • Patent number: 9406642
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate; a plain trace on the substrate; an insulated trace on the substrate; an insulation layer on the insulated trace, the insulation layer at least partially covers the insulated trace; and a semiconductor device over the substrate, the semiconductor device has a plain bump attached on the plain trace and an inner bump attached on the insulated trace, and the plain bump is mounted adjacent to the insulation layer.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: August 2, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: HeeJo Chi, Bartholomew Liao Chung Foh, Sheila Marie L. Alvarez, Zigmund Ramirez Camacho, Dao Nguyen Phu Cuong
  • Patent number: 9355993
    Abstract: A system and method of manufacture of an integrated circuit system includes: a die having a via, the die having a top side and a bottom side; a top interconnect mounted to the via at the top side; an interconnect pillar mounted to the via at the bottom side; a device interconnect mounted to the interconnect pillar; and a base adhesive covering the interconnect pillar and the device interconnect.
    Type: Grant
    Filed: July 3, 2015
    Date of Patent: May 31, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Won Kyoung Choi, Pandi Chelvam Marimuthu
  • Patent number: 9355983
    Abstract: A system and a method of manufacture thereof of integrated circuit packaging system, including: a pillar; a conductive buildup attached to the pillar; and a molded body encapsulating the conductive buildup, the pillar extending out of the molded body.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: May 31, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Bartholomew Liao Chung Foh, Dao Nguyen Phu Cuong, Jeffrey David Punzalan
  • Patent number: 9355962
    Abstract: A method of manufacture of an integrated circuit package stacking system including: forming a base frame includes: providing a support panel, and forming a coupling pad, a mounting pad, a base frame trace, a discrete component pad, or a combination thereof on the support panel; fabricating a package substrate; coupling an integrated circuit die to the package substrate; mounting the base frame over the integrated circuit die and the package substrate; and removing the support panel from the base frame.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: May 31, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: SeongMin Lee, Sungmin Song, Jong-Woo Ha
  • Patent number: 9355939
    Abstract: A method of manufacture of an integrated circuit package system includes: providing a base package substrate including: forming component contacts on a component side of the base package substrate, forming system contacts on a system side of the base package substrate, and forming a reference voltage circuit between the component contacts and the system contacts; mounting a first integrated circuit die on the component contacts; mounting a lead frame on the first integrated circuit die and coupled to the component contacts; and isolating a conductive shield from the lead frame, the conductive shield coupled to the reference voltage circuit.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: May 31, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: NamJu Cho, HeeJo Chi, HanGil Shin
  • Patent number: 9349666
    Abstract: An integrated circuit packaging system includes: providing a base substrate; applying a molded under-fill on the base substrate; forming a substrate contact extender through the molded under-fill and in direct contact with the base substrate; mounting a stack device over the molded under-fill; attaching a coupling connector from the substrate contact extender to the stack device; and forming a base encapsulation on the stack device, the substrate contact extender, and encapsulating the coupling connector.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: May 24, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: JoHyun Bae, In Sang Yoon, DaeSik Choi
  • Patent number: 9331003
    Abstract: An integrated circuit packaging system, and method of manufacture thereof, includes: lead islands; a pre-molded material surrounding a bottom of the lead islands; a device over a portion of the lead islands and having electrical connections to another portion of the lead islands, the electrical connections over areas of the another portion of the lead islands over areas covered by the pre-molded material; and an encapsulation over the device and the lead islands.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 3, 2016
    Assignee: STATS ChipPac Ltd.
    Inventors: Zigmund Ramirez Camacho, Bartholomew Liao Chung Foh, Sheila Marie L. Alvarez, Dao Nguyen Phu Cuong, HeeJo Chi
  • Patent number: 9330945
    Abstract: An integrated circuit package system with multi-chip module is provided including: providing an upper substrate having an upper chip thereon; positioning a lower chip under the upper chip, the lower chip having bottom interconnects thereon; encapsulating the upper chip and the lower chip with a chip encapsulant on the upper substrate with the bottom interconnects exposed; mounting the lower chip over a lower substrate with a gap between the chip encapsulant and the lower substrate; and filling the gap with a package encapsulant or chip attach adhesive.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: May 3, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Sungmin Song, SeungYun Ahn, JoHyun Bae, Jong-Woo Ha
  • Patent number: 9324641
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a routable distribution layer on a leadframe; mounting an integrated circuit over the routable distribution layer; encapsulating with an encapsulation over the routable distribution layer; peeling the leadframe away from the routable distribution layer with a bottom distribution side of the routable distribution layer exposed from the encapsulation; and mounting an external interconnect on the routable distribution layer.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: April 26, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 9324673
    Abstract: A method of manufacture of an integrated circuit packaging system includes: removing a portion of a leadframe to form a partially removed region and an upper portion of a peripheral lead on the leadframe first side; mounting a first integrated circuit over the partially removed region with a first adhesive; forming a first molding layer directly on the first integrated circuit and the peripheral lead; removing a portion of a leadframe second side exposing the first adhesive; mounting a second integrated circuit on the first adhesive of the first integrated circuit; forming a first interconnection layer directly on the first integrated circuit with the first integrated circuit and the peripheral lead electrically connected; and forming a second interconnection layer directly on the second integrated circuit with the second integrated circuit and the peripheral lead electrically connected.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: April 26, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventor: Zigmund Ramirez Camacho
  • Patent number: 9324584
    Abstract: System and method of manufacturing an integrated circuit packaging system using transferable trace lead frame. A lead frame is provided having lower metal contacts. A masking layer can be formed on an upper surface of the lead frame for protection and shielding purposes. Routing layer and conductive lands may subsequently be formed by shaping the lead frame, along with bottom encapsulation. The masking layer may subsequently be removed for additional processing steps including connecting an integrated circuit die to the upper surface of the lead frame.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: April 26, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 9318403
    Abstract: An integrated circuit packaging system including: connecting a first integrated circuit device and a package substrate; attaching a support bump to the package substrate; providing a second integrated circuit device having an inner encapsulation; applying a magnetic film on the inner encapsulation of the second integrated circuit device; and mounting the second integrated circuit device over the first integrated circuit device with the magnetic film on the first integrated circuit device and the support bump.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: April 19, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Sung Soo Kim, DongSik Kim, ChoongHwan Kwon
  • Patent number: 9312194
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting platform; applying an attach layer on the mounting platform; mounting an integrated circuit die on the attach layer; forming an encapsulation on the integrated circuit die and the attach layer, the mounting platform exposed from the encapsulation; and forming a terminal having a terminal protrusion from the leadframe, the terminal protrusion below a horizontal plane of the mounting platform.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: April 12, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 9305809
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: discrete components coupled to a top trace; vias attached to the top trace separated from the discrete components; a dielectric layer on the top trace, the discrete components, and the vias, includes a component surface formed above the discrete components, with the top trace coplanar with the dielectric layer; and system interconnects coupled to the vias for electrically connecting the top trace, the discrete components, or a combination thereof to the system interconnects.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: April 5, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Emmanuel Espiritu, Allan Pumatong Ilagan, Jeffrey David Punzalan
  • Patent number: 9305873
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion, the contact protrusion having a lower protrusion surface, an upper protrusion surface, and a protrusion sidewall; forming a die paddle, adjacent to the isolated contact, having a die paddle protrusion, the die paddle protrusion having a lower die protrusion surface, an upper die protrusion surface, and a die protrusion sidewall; depositing a contact pad on the contact protrusion; depositing a die paddle pad on the die paddle protrusion; coupling an integrated circuit die to the contact protrusion; and molding an encapsulation on the integrated circuit die.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: April 5, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 9299650
    Abstract: An integrated circuit packaging system and method of manufacture thereof including: a base substrate; an integrated circuit die on the base substrate; vertical interconnects attached to the base substrate around the integrated circuit die; and a single metal layer interposer mounted on the vertical interconnects, the single metal layer interposer including: a routing pattern having interposer contacts and traces, and a dielectric layer on the interposer contacts and traces, a top surface of the interposer contacts coplanar with a top surface of the dielectric layer.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: March 29, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: HeeJo Chi, HanGil Shin, NamJu Cho, Kyung Moon Kim
  • Patent number: 9299648
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a component side and a system side; depositing a solder resist layer on the component side of the package substrate; patterning groups of access openings and a die mount opening in the solder resist layer; attaching an integrated circuit die in the die mount opening; forming conductive contacts in the access openings; and attaching system interconnects to the system side of the package substrate including controlling a coplanarity of the system interconnects by the solder resist layer.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: March 29, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Il Kwon Shim, Seng Guan Chow, Heap Hoe Kuan
  • Patent number: 9299644
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a terminal having a top with a depression; applying a dielectric material in the depression, the dielectric material having a gap formed therein and exposing a portion of the top therefrom; forming a trace within the gap and in direct contact with the top, the trace extending laterally over an upper surface of the dielectric material; and connecting an integrated circuit to the terminal through the trace.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: March 29, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Trasporto, Zigmund Ramirez Camacho
  • Patent number: 9293351
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a partially removed portion including: a conductive pattern having a lower surface on a top frame surface of the leadframe, a contact protrusion and a support lead on the lower surface of the conductive pattern, the support lead for supporting the partially removed portion of the leadframe during an encapsulation process, and a contact pad on a bottom surface of the contact protrusion; mounting an integrated circuit die above the conductive pattern; applying an encapsulation on the integrated circuit die and the conductive pattern, the lower surface of the conductive pattern exposed from the encapsulation; and removing at least a portion of the leadframe to form a contact lead and expose a bottom surface of the encapsulation.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: March 22, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua, Emmanuel Espiritu
  • Patent number: 9293385
    Abstract: An integrated circuit package system includes: providing an internal device; encapsulating the internal device with an encapsulation having an outer surface; and forming a redistribution line having connection points on the outer surface of the encapsulation.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: March 22, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Reza Argenty Pagaila, Byung Tai Do, Dioscoro A. Merilo