Patents Assigned to Stats Chippac Ltd.
  • Patent number: 9293350
    Abstract: A method of manufacturing a semiconductor package system includes: providing a first substrate; providing a second substrate having a cavity, the second substrate being attached to the first substrate; connecting the first substrate to the second substrate using an interconnect, the interconnect being in the cavity; and attaching a semiconductor device to the first substrate or the second substrate.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: March 22, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Seng Guan Chow, Rui Huang, Heap Hoe Kuan
  • Patent number: 9293401
    Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: March 22, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Seung Wook Yoon, Jose A. Caparas, Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Xusheng Bao, Jianmin Fang
  • Patent number: 9293349
    Abstract: A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground point. A plurality of semiconductor die is mounted to the substrate over the ground shield. The ground shield extends beyond a footprint of the plurality of semiconductor die. An encapsulant is formed over the plurality of semiconductor die and substrate. Dicing channels are formed in the encapsulant, between the plurality of semiconductor die, and over the ground shield. A plurality of metal-filled holes is formed along the dicing channels, and extends into the substrate and through the ground shield. A top shield is formed over the plurality of semiconductor die and electrically and mechanically connects to the ground shield through the metal-filled holes. The top and ground shields are configured to block electromagnetic interference generated with respect to an integrated passive device disposed in the semiconductor die.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: March 22, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: OhHan Kim, SunMi Kim, KyungHoon Lee
  • Patent number: 9293385
    Abstract: An integrated circuit package system includes: providing an internal device; encapsulating the internal device with an encapsulation having an outer surface; and forming a redistribution line having connection points on the outer surface of the encapsulation.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: March 22, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Reza Argenty Pagaila, Byung Tai Do, Dioscoro A. Merilo
  • Patent number: 9287204
    Abstract: A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: March 15, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: KyungMoon Kim, KooHong Lee, JaeHak Yee, YoungChul Kim, Lan Hoang, Pandi C. Marimuthu, Steve Anderson, HunTeak Lee, HeeJo Chi
  • Publication number: 20160071813
    Abstract: A semiconductor device has a semiconductor die with a die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow.
    Type: Application
    Filed: November 9, 2015
    Publication date: March 10, 2016
    Applicant: STATS CHIPPAC, LTD.
    Inventor: Rajendra D. Pendse
  • Patent number: 9281274
    Abstract: An integrated circuit substrate via system, and method of manufacture therefor, includes: a substrate having a substrate via in the substrate; a buffer layer patterned over the substrate via, the buffer layer having a planar surface; and a substrate via cap patterned over the buffer layer, the substrate via cap having a planar surface based on the planar surface of the buffer layer.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: March 8, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Xing Zhao, Chang Bum Yong, Duk Ju Na, Kyaw Oo Aung, Ling Ji
  • Patent number: 9281300
    Abstract: A semiconductor package includes a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the BGA substrate, and an application die attached to the IPD. A method of manufacturing a semiconductor package includes providing a BGA substrate having integrated metal layer circuitry, attaching a flip chip CSMP having a first IPD to the BGA substrate, and attaching an application die to the IPD.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: March 8, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Leo A. Merilo, Emmanuel A. Espiritu, Dario S. Filoteo, Jr., Rachel L. Abinan
  • Patent number: 9281259
    Abstract: A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses can be formed by removing a portion of the first encapsulant. Alternatively, the recesses are formed in a chase mold having a plurality of extended surfaces. A second encapsulant can be deposited into the recesses of the first encapsulant. The carrier is removed and an interconnect structure is formed over the semiconductor die and first encapsulant. The thickness of the first encapsulant provides sufficient stiffness to reduce warpage while the recesses provide stress relief during formation of the interconnect structure. A portion of the first encapsulant and recesses are removed to reduce thickness of the semiconductor device.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: March 8, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jose Alvin Caparas, Glenn Omandam
  • Patent number: 9281228
    Abstract: A semiconductor device has a semiconductor die mounted to a substrate. A recess is formed in a back surface of the semiconductor die to an edge of the semiconductor die with sidewalls on at least two sides of the semiconductor die. The sidewalls are formed by removing a portion of the back surface of the die, or by forming a barrier layer on at least two sides of the die. A channel can be formed in the back surface of the semiconductor die to contain the TIM. A TIM is formed in the recess. A heat spreader is mounted in the recess over the TIM with a down leg portion of the heat spreader thermally connected to the substrate. The sidewalls contain the TIM to maintain uniform coverage of the TIM between the heat spreader and back surface of the semiconductor die.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: March 8, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: DaeSik Choi, JoungIn Yang, MinJung Kim, Sang Mi Park, MinWook Yu
  • Patent number: 9279673
    Abstract: A warpage test system uses a calibration block to calibrate the warpage test system over a temperature profile. The calibration block includes a first metal block bonded to a second metal block. The first metal block includes a first metal and a second different metal. The first metal block includes a CTE different than a CTE of the second metal block. The calibration block is disposed in the warpage test system. A warpage of the calibration block is measured over a temperature profile ranging from 28° C. to 260° C. A deviation between the measured warpage of the calibration block and a known thermal expansion of the calibration block over the temperature profile is recorded. The warpage measurement in a semiconductor package is compensated by the deviation between the measured warpage of the calibration block and the known thermal expansion or warpage of the calibration block over the temperature profile.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: March 8, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: WonJun Ko, SeungYong Chai, OhHan Kim, GwangTae Kim, Kenny Lee
  • Patent number: 9275877
    Abstract: A semiconductor device has a first insulating layer formed over a carrier. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer. Vias are formed through the second insulating layer. A second conductive layer is formed over the second insulating layer and extends into the vias. A semiconductor die is mounted to the second conductive layer. A bond wire is formed between a contact pad on the semiconductor die and the second conductive layer. The second conductive layer extends to a mounting site of the semiconductor die to minimize the bond wire span. An encapsulant is deposited over the semiconductor die. A portion of the first insulating layer is removed to expose the second conductive layer. A portion of the first conductive layer is removed to electrically isolate remaining portions of the first conductive layer.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: March 1, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Rui Huang, Heap Hoe Kuan, Seng Guan Chow
  • Patent number: 9269598
    Abstract: A semiconductor device has a first conductive layer formed over a sacrificial substrate. A first integrated passive device (IPD) is formed in a first region over the first conductive layer. A conductive pillar is formed over the first conductive layer. A high-resistivity encapsulant greater than 1.0 kohm-cm is formed over the first IPD to a top surface of the conductive pillar. A second IPD is formed over the encapsulant. The first encapsulant has a thickness of at least 50 micrometers to vertically separate the first and second IPDs. An insulating layer is formed over the second IPD. The sacrificial substrate is removed and a second semiconductor die is disposed on the first conductive layer. A first semiconductor die is formed in a second region over the substrate. A second encapsulant is formed over the second semiconductor die and a thermally conductive layer is formed over the second encapsulant.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: February 23, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Jianmin Fang, Kang Chen, Haijing Cao
  • Patent number: 9269691
    Abstract: A semiconductor device has a semiconductor die. The semiconductor die is disposed over a conductive substrate. An encapsulant is deposited over the semiconductor die. A first interconnect structure is formed over the encapsulant. An opening is formed through the substrate to isolate a portion of the substrate electrically connected to the first interconnect structure. A bump is formed over the first interconnect structure. Conductive vias are formed through the encapsulant and electrically connected to the portion of the substrate. A plurality of bumps is formed over the semiconductor die. A first conductive layer is formed over the encapsulant. A first insulating layer is formed over the first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. Protrusions extend above the substrate.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: February 23, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: HeeJo Chi, HanGil Shin, NamJu Cho
  • Patent number: 9269595
    Abstract: A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The active surface of the first semiconductor die is oriented toward an active surface of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of a back surface of the second semiconductor die opposite the active surface is removed. Conductive pillars are formed around the second semiconductor die. TSVs can be formed through the first semiconductor die. An interconnect structure is formed over the back surface of the second semiconductor die, encapsulant, and conductive pillars. The interconnect structure is electrically connected to the conductive pillars. A portion of a back surface of the first semiconductor die opposite the active surface is removed. A heat sink or shielding layer can be formed over the back surface of the first semiconductor die.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: February 23, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: HeeJo Chi, NamJu Cho, HanGil Shin
  • Patent number: 9263332
    Abstract: A semiconductor device is made by mounting a semiconductor wafer to a temporary carrier. A plurality of TSV is formed through the wafer. A cavity is formed partially through the wafer. A first semiconductor die is mounted to a second semiconductor die. The first and second die are mounted to the wafer such that the first die is disposed over the wafer and electrically connected to the TSV and the second die is disposed within the cavity. An encapsulant is deposited over the wafer and first and second die. A portion of the encapsulant is removed to expose a first surface of the first die. A portion of the wafer is removed to expose the TSV and a surface of the second die. The remaining portion of the wafer operates as a TSV interposer for the first and second die. An interconnect structure is formed over the TSV interposer.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: February 16, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: HeeJo Chi, NamJu Cho, HanGil Shin
  • Patent number: 9263361
    Abstract: A semiconductor device is made by forming a conductive layer over a temporary carrier. The conductive layer includes a wettable pad. A stud bump is formed over the wettable pad. The stud bump can be a stud bump or stacked bumps. A semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the stud bump. A first interconnect structure is formed over a first surface of the encapsulant. The first interconnect structure includes a first IPD and is electrically connected to the stud bump. The carrier is removed. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The second interconnect structure includes a second IPD. The first or second IPD includes a capacitor, resistor, or inductor. The semiconductor devices are stackable and electrically connected through the stud bump.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: February 16, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Byung Tai Do, Shuangwu Huang, Rajendra D. Pendse
  • Publication number: 20160043047
    Abstract: A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package.
    Type: Application
    Filed: July 31, 2015
    Publication date: February 11, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Il Kwon Shim, Pandi C. Marimuthu, Won Kyoung Choi, Sze Ping Goh, Jose A. Caparas
  • Patent number: 9257384
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a stack substrate over the base substrate with an inter-substrate connector directly on the stack substrate and the base substrate, the inter-substrate connector having an inter-substrate connector pitch; mounting an integrated circuit over the stack substrate, the integrated circuit having an internal connector directly on the stack substrate; and attaching an external connector directly on the base substrate, the external connector having an external connector pitch greater than the inter-substrate connector pitch.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: February 9, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Soohan Park, Sung Jun Yoon
  • Patent number: 9257356
    Abstract: A semiconductor device has a conductive layer formed on a substrate. The conductive layer has a first portion constituting contact pads and a second portion constituting an integrated passive device such as an inductor. A spacer is formed on the substrate around the second portion of the conductive layer. The spacer can be insulating material or conductive material for shielding. A semiconductor die is mounted to the spacer. An electrical connection is formed between contact pads on the semiconductor die and the contact pads on the substrate. An encapsulant is formed around the semiconductor die, electrical connections, spacer, and conductive layer. The substrate is removed to expose the conductive layer. An interconnect structure is formed on the backside of the substrate. The interconnect structure is electrically connected to the conductive layer. The semiconductor device can be integrated into a package.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: February 9, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Rui Huang, Heap Hoe Kuan, Yaojian Lin, Seng Guan Chow