Patents Assigned to Stats Chippac Ltd.
  • Patent number: 9257357
    Abstract: A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: February 9, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Frederick R. Dahilig, Zigmund R. Camacho, Lionel Chien Hui Tay, Dioscoro A. Merilo
  • Patent number: 9257382
    Abstract: A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. An insulating lining is formed around the conductive vias and a conductive layer is formed over the insulating lining. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the first insulating layer is removed and a second portion of the first insulating layer remains as guard rings around the conductive vias. A conductive layer is formed over the conductive vias. A second insulating layer is formed over the surface of the semiconductor wafer, guard rings, and conductive vias. A portion of the second insulating layer is removed to expose the conductive vias and a portion of the guard rings.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: February 9, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Duk Ju Na, Lai Yee Chia, Chang Beom Yong
  • Patent number: 9258904
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: February 9, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 9257411
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the first semiconductor die. A penetrable adhesive layer is formed over a temporary carrier. The adhesive layer can include a plurality of slots. The semiconductor die is mounted to the carrier by embedding the bumps into the penetrable adhesive layer. The semiconductor die and interconnect structure can be separated by a gap. An encapsulant is deposited over the first semiconductor die. The bumps embedded into the penetrable adhesive layer reduce shifting of the first semiconductor die while depositing the encapsulant. The carrier is removed. An interconnect structure is formed over the semiconductor die. The interconnect structure is electrically connected to the bumps. A thermally conductive bump is formed over the semiconductor die, and a heat sink is mounted to the interconnect structure and thermally connected to the thermally conductive bump.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: February 9, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, JunMo Koo
  • Patent number: 9252094
    Abstract: A semiconductor device has a semiconductor die with a first conductive layer formed over an active surface of the semiconductor die. An insulation layer is formed over the active surface of the semiconductor die. A second conductive layer is conformally applied over the insulating layer and first conductive layer. Conductive pillars are formed over the first conductive layer. Conductive rings are formed around a perimeter of the conductive pillars. A conductive material is deposited over the surface of the conductive pillars within the conductive rings. A substrate has a third conductive layer formed over a surface of the substrate. The semiconductor die is mounted to a substrate with the third conductive layer electrically connected to the conductive material within the conductive rings. The conductive rings inhibit outward flow of the conductive material from under the conductive pillars to prevent electrical bridging between adjacent conductive pillars.
    Type: Grant
    Filed: April 30, 2011
    Date of Patent: February 2, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: DaeSik Choi, Sang Mi Park
  • Patent number: 9252075
    Abstract: A semiconductor device is made from a semiconductor wafer containing semiconductor die separated by a peripheral region. A conductive via-in-via structure is formed in the peripheral region or through an active region of the device to provide additional tensile strength. The conductive via-in-via structure includes an inner conductive via and outer conductive via separated by insulating material. A middle conductive via can be formed between the inner and outer conductive vias. The inner conductive via has a first cross-sectional area adjacent to a first surface of the semiconductor device and a second cross-sectional area adjacent to a second surface of the semiconductor device. The outer conductive via has a first cross-sectional area adjacent to the first surface of the semiconductor device and a second cross-sectional area adjacent to the second surface of the semiconductor device. The first cross-sectional area is different from the second cross-sectional area.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: February 2, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Lionel Chien Hui Tay, Jianmin Fang, Zigmund R. Camacho
  • Patent number: 9252092
    Abstract: A semiconductor device includes a semiconductor die and an encapsulant formed over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A plurality of conductive vias is formed through the first insulating layer. A conductive pad is formed over the encapsulant. An interconnect structure is formed over the semiconductor die and encapsulant. A first opening is formed in the encapsulant to expose the conductive vias. The conductive vias form a conductive via array. The conductive via array is inspected through the first opening to measure a dimension of the first opening and determine a position of the first opening. The semiconductor device is adjusted based on a position of the conductive via array. A conductive material is formed in the first opening over the conductive via array.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: February 2, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kang Chen, Yu Gu
  • Patent number: 9252066
    Abstract: A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: February 2, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Il Kwon Shim, Yaojian Lin, Seng Guan Chow
  • Patent number: 9252032
    Abstract: A semiconductor wafer contains a plurality of first semiconductor die. The semiconductor wafer is mounted to a carrier. A channel is formed through the semiconductor wafer to separate the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. An encapsulant is deposited over the carrier and first semiconductor die and into the channel while a side portion and surface portion of the second semiconductor die remain exposed from the encapsulant. A first conductive via is formed through the encapsulant in the channel. A second conductive via is formed through the encapsulant over a contact pad of the first semiconductor die. A conductive layer is formed over the encapsulant between the first and second conductive vias. An insulating layer is formed over the conductive layer and encapsulant. The carrier is removed. An interconnect structure is formed over the first conductive via.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: February 2, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: DaeSik Choi, WonJun Ko, JaEun Yun
  • Patent number: 9252172
    Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: February 2, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Seng Guan Chow, Lee Sun Lim, Rui Huang, Xusheng Bao, Ma Phoo Pwint Hlaing
  • Patent number: 9252130
    Abstract: Methods of producing a semiconductor package using dual-sided thermal compression bonding includes providing a substrate having an upper surface and a lower surface. A first device having a first surface and a second surface can be provided along with a second device having a third surface and a fourth surface. The first surface of the first device can be coupled to the upper surface of the substrate while the third surface of the second device can be coupled to the lower surface of the substrate, the coupling occurring simultaneously to produce the semiconductor package.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: February 2, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: KyungMoon Kim, YoungChul Kim, HunTeak Lee, KeonTaek Kang, HeeJo Chi
  • Patent number: 9252093
    Abstract: A semiconductor wafer has a contact pad. A first insulating layer is formed over the wafer. A second insulating layer is formed over the first insulating layer and contact pad. A portion of the second insulating layer is removed to expose the contact pad. A first UBM layer is formed over and follows a contour of the second insulating layer and contact pad to create a well over the contact pad. A first buffer layer is formed in the well over the first UBM layer and the contact pad. A second UBM layer is formed over the first UBM layer and first buffer layer. A third UBM layer is formed over the second UBM layer. A bump is formed over the third UBM layer. The first buffer layer reduces stress on the bump and contact pad. A second buffer layer can be formed between the second and third UBM layers.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: February 2, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: DaeSik Choi, JoonYoung Choi, Wonll Kwon
  • Patent number: 9245772
    Abstract: A semiconductor package comprises a substrate, a first semiconductor die mounted to the substrate, and a first double side mold (DSM) internal stackable module (ISM) bonded directly to the first semiconductor die through a first adhesive. The first DSM ISM includes a first molding compound, and a second semiconductor die disposed in the first molding compound. The semiconductor package further comprises a first electrical connection coupled between the first semiconductor die and the substrate, and a second electrical connection coupled between the first DSM ISM and the substrate.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: January 26, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: JoungIn Yang, ChoongBin Yim, KeonTeak Kang, YoungChul Kim
  • Patent number: 9245834
    Abstract: A semiconductor device has a semiconductor die. The semiconductor die has a contact pad. A first conductive layer is formed over the contact pad. A conductive shell having a hollow core is formed over the first conductive layer. A compliant material is deposited in the hollow core. The semiconductor die is mounted over a substrate with the conductive shell electrically connected to a conductive trace on the substrate. A second conductive layer is formed over the conductive shell. The compliant material is an insulating material. A bump material is deposited around the conductive shell. A pre-solder material is deposited over the conductive trace. The conductive shell has a cross-sectional width less than 7 micrometers. The second conductive layer is a conductive lip. Mounting the semiconductor die over the substrate further includes mounting the semiconductor die over the substrate in a bump on lead (BOL) configuration.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: January 26, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Ming-Che Hsieh
  • Patent number: 9245770
    Abstract: A semiconductor device has a semiconductor die disposed over a substrate. The semiconductor die and substrate are placed in a chase mold. An encapsulant is deposited over and between the semiconductor die and substrate simultaneous with bonding the semiconductor die to the substrate in the chase mold. The semiconductor die is bonded to the substrate using thermocompression by application of force and elevated temperature. An electrical interconnect structure, such as a bump, pillar bump, or stud bump, is formed over the semiconductor die. A flux material is deposited over the interconnect structure. A solder paste or SOP is deposited over a conductive layer of the substrate. The flux material and SOP provide temporary bond between the semiconductor die and substrate. The interconnect structure is bonded to the SOP. Alternatively, the interconnect structure can be bonded directly to the conductive layer of the substrate, with or without the flux material.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: January 26, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: KyungMoon Kim, KooHong Lee, JaeHak Yee, YoungChul Kim, Lan Hoang, Pandi C. Marimuthu, Steve Anderson, HeeJo Chi
  • Patent number: 9240380
    Abstract: A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: January 19, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Seng Guan Chow, Seung Uk Yoon
  • Patent number: 9240331
    Abstract: A semiconductor device includes a substrate with contact pads. A mask is disposed over the substrate. Aluminum-wettable conductive paste is printed over the contact pads of the substrate. A semiconductor die is disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure over the contact pads of the substrate. The contact pads include aluminum. Contact pads of the semiconductor die are disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure between the contact pads of the semiconductor die and the contact pads of the substrate. The interconnect structure is formed directly on the contact pads of the substrate and semiconductor die. The contact pads of the semiconductor die are etched prior to reflowing the aluminum-wettable conductive paste. An epoxy pre-dot to maintain a separation between the semiconductor die and substrate.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: January 19, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: KyungMoon Kim, KooHong Lee, JaeHak Yee, YoungChul Kim, Lan Hoang, Pandi C. Marimuthu, Steve Anderson, See Chian Lim, HeeJo Chi
  • Patent number: 9240384
    Abstract: A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. The second insulating layer has a sidewall between a surface of the second insulating material and surface of the second conductive layer. A protective layer is formed over the second insulating layer and surface of the second conductive layer. The protective layer follows a contour of the surface and sidewall of the second insulating layer and second conductive layer. A bump is formed over the surface of the second conductive layer and a portion of the protective layer adjacent to the second insulating layer. The protective layer protects the second insulating layer.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: January 19, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Qing Zhang, Haijing Cao
  • Publication number: 20160013148
    Abstract: A semiconductor device has a build-up interconnect structure including a first insulating layer with a first material and a second insulating layer with a second material. A first conductive layer is formed over the first insulating layer, and the second insulating layer is formed over the first conductive layer. An optional third insulating layer has the second material and is formed over the second insulating layer. A fourth insulating layer has the first material and is formed over the third insulating layer. The second, third, and fourth insulating layers are cured sequentially or simultaneously. The first material includes a greater tensile strength, elastic modulus, and CTE than the second material. The build-up interconnect structure is formed over a semiconductor wafer or semiconductor die in a reconstituted panel. Alternatively, the build-up interconnect structure is formed over a carrier and a semiconductor die is mounted over the build-up interconnect structure.
    Type: Application
    Filed: September 22, 2015
    Publication date: January 14, 2016
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Yaojian Lin, Kang Chen
  • Patent number: 9236352
    Abstract: A semiconductor wafer has a plurality of semiconductor die. A peripheral region is formed around the die. An insulating material is formed in the peripheral region. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. A conductive layer is formed between the conductive THV and contact pads of the semiconductor die. A noise absorbing material is deposited in the peripheral region between the conductive THV to isolate the semiconductor die from intra-device interference. The noise absorbing material extends through the peripheral region from a first side of the semiconductor die to a second side of the semiconductor die. The noise absorbing material has an angular, semi-circular, or rectangular shape. The noise absorbing material can be dispersed in the peripheral region between the conductive THV.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: January 12, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Byung Tai Do, Shuangwu Huang, Nathapong Suthiwongsunthorn, Dioscoro Merilo