Patents Assigned to Stats Chippac Ltd.
  • Patent number: 10297518
    Abstract: A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure. A second supporting layer is formed over the first supporting layer and includes a fiber enhanced polymer composite material comprising a footprint including an area greater than or equal to an area of a footprint of the semiconductor die. The semiconductor die comprises a thickness less than 450 micrometers (?m). The thickness of the semiconductor die is at least 1 ?m less than a difference between a total thickness of the semiconductor device and a thickness of the build-up interconnect structure and the second supporting layer.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: May 21, 2019
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kang Chen, Yu Gu
  • Publication number: 20160351486
    Abstract: A semiconductor device comprises a first conductive layer. A second conductive layer is formed over the first conductive layer. A semiconductor component is disposed over the first conductive layer. The second conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component. A third conductive layer is formed over the semiconductor component opposite the first conductive layer. The semiconductor device includes a symmetrical structure. A first insulating layer is formed between the first conductive layer and semiconductor component. A second insulating layer is formed between the semiconductor component and third conductive layer. A height of the first insulating layer between the first conductive layer and semiconductor component is between 90% and 110% of a height of the second insulating layer between the semiconductor component and third conductive layer. The semiconductor component includes a passive device.
    Type: Application
    Filed: May 27, 2015
    Publication date: December 1, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventors: JinHee Jung, HyungSang Park, SungSoo Kim
  • Publication number: 20160300797
    Abstract: A semiconductor device comprises a first conductive layer formed on a carrier over an insulating layer. A portion of the insulating layer is removed prior to forming the first conductive layer. A first semiconductor die is disposed over the first conductive layer. A discrete electrical component is disposed over the first conductive layer adjacent to the first semiconductor die. A first encapsulant is deposited over the first conductive layer and first semiconductor layer. A conductive pillar is formed through the first encapsulant between the first conductive layer and second conductive layer. A second encapsulant is deposited around the first encapsulant, first conductive layer, and first semiconductor die. A second conductive layer is formed over the first semiconductor die, first encapsulant, and second encapsulant opposite the first conductive layer. The carrier is removed after forming the second conductive layer. A semiconductor package is mounted to the first conductive layer.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 13, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Il Kwon Shim, Pandi C. Marimuthu, Yaojian Lin
  • Publication number: 20160300817
    Abstract: A semiconductor device comprises a first semiconductor package including a first interconnect structure extending over a surface of the first semiconductor package. The first semiconductor package includes an interposer and a second semiconductor die disposed over the interposer. A second encapsulant is deposited over the interposer and second semiconductor die. A first semiconductor die is disposed over the surface of the first semiconductor package. A second interconnect structure extends from the first semiconductor die opposite the first semiconductor package. A first encapsulant is deposited over the first semiconductor package and first semiconductor die. A portion of the first encapsulant over the first interconnect structure and second interconnect structure is removed. A discrete component is disposed on the surface of the first semiconductor package. A build-up interconnect structure is formed over the first semiconductor package and first semiconductor die.
    Type: Application
    Filed: March 28, 2016
    Publication date: October 13, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto
  • Publication number: 20160276307
    Abstract: A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.
    Type: Application
    Filed: March 17, 2015
    Publication date: September 22, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventor: Yaojian Lin
  • Publication number: 20160233168
    Abstract: A semiconductor device has a plurality of semiconductor die. A substrate is provided with bumps disposed over the substrate. A first prefabricated insulating film is disposed between the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The bumps include a copper core encapsulated within copper plating. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The substrate includes a conductive layer formed in the substrate and coupled to the bumps. The semiconductor die is disposed between the bumps of the substrate. The bumps and the semiconductor die are embedded within the first prefabricated insulating film. A portion of the first prefabricated insulating film is removed to expose the bumps. The bumps electrically connect the substrate to the interconnect structure.
    Type: Application
    Filed: April 15, 2016
    Publication date: August 11, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventors: HeeJo Chi, HanGil Shin, NamJu Cho
  • Patent number: 9406642
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate; a plain trace on the substrate; an insulated trace on the substrate; an insulation layer on the insulated trace, the insulation layer at least partially covers the insulated trace; and a semiconductor device over the substrate, the semiconductor device has a plain bump attached on the plain trace and an inner bump attached on the insulated trace, and the plain bump is mounted adjacent to the insulation layer.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: August 2, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: HeeJo Chi, Bartholomew Liao Chung Foh, Sheila Marie L. Alvarez, Zigmund Ramirez Camacho, Dao Nguyen Phu Cuong
  • Publication number: 20160218089
    Abstract: A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. An insulating layer is formed over the encapsulant and a first surface of the semiconductor die. A semiconductor component is disposed over the insulating layer and first surface of the semiconductor die. A first interconnect structure is formed over the encapsulant and first surface of the semiconductor die to embed the semiconductor component. A conductive via is formed in the semiconductor die. A heat sink is formed over the semiconductor die. A second interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the semiconductor component. An opening is formed in the insulating layer.
    Type: Application
    Filed: April 1, 2016
    Publication date: July 28, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventors: KyungHoon Lee, HyunJin Song, KyoungIl Huh, DaeSik Choi
  • Publication number: 20160214857
    Abstract: A microelectromechanical system (MEMS) semiconductor device has a first and second semiconductor die. A first semiconductor die is embedded within an encapsulant together with a modular interconnect unit. Alternatively, the first semiconductor die is embedded within a substrate. A second semiconductor die, such as a MEMS die, is disposed over the first semiconductor die and electrically connected to the first semiconductor die through an interconnect structure. In another embodiment, the first semiconductor die is flip chip mounted to the substrate, and the second semiconductor die is wire bonded to the substrate adjacent to the first semiconductor die. In another embodiment, first and second semiconductor die are embedded in an encapsulant and are electrically connected through a build-up interconnect structure. A lid is disposed over the semiconductor die. In a MEMS microphone embodiment, the lid, substrate, or interconnect structure includes an opening over a surface of the MEMS die.
    Type: Application
    Filed: January 27, 2016
    Publication date: July 28, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Il Kwon Shim
  • Publication number: 20160197059
    Abstract: A semiconductor device is made by providing a substrate, forming a first insulation layer over the substrate, forming a first conductive layer over the first insulation layer, forming a second insulation layer over the first conductive layer, and forming a second conductive layer over the second insulation layer. A portion of the second insulation layer, first conductive layer, and second conductive layer form an integrated passive device (IPD). The IPD can be an inductor, capacitor, or resistor. A plurality of conductive pillars is formed over the second conductive layer. One conductive pillar removes heat from the semiconductor device. A third insulation layer is formed over the IPD and around the plurality of conductive pillars. A shield layer is formed over the IPD, third insulation layer, and conductive pillars. The shield layer is electrically connected to the conductive pillars to shield the IPD from electromagnetic interference.
    Type: Application
    Filed: March 14, 2016
    Publication date: July 7, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Jianmin Fang, Kang Chen, Haijing Cao
  • Publication number: 20160197022
    Abstract: A semiconductor wafer contains a plurality of semiconductor die each having a plurality of contact pads. A sacrificial adhesive is deposited over the contact pads. Alternatively, the sacrificial adhesive is deposited over the carrier. An underfill material can be formed between the contact pads. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier such that the sacrificial adhesive is disposed between the contact pads and temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and sacrificial adhesive is removed to leave a via over the contact pads. An interconnect structure is formed over the encapsulant. The interconnect structure includes a conductive layer which extends into the via for electrical connection to the contact pads. The semiconductor die is offset from the interconnect structure by a height of the sacrificial adhesive.
    Type: Application
    Filed: March 11, 2016
    Publication date: July 7, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Publication number: 20160163675
    Abstract: A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate.
    Type: Application
    Filed: February 1, 2016
    Publication date: June 9, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventors: KyungMoon Kim, KooHong Lee, JaeHak Yee, YoungChul Kim, Lan Hoang, Pandi C. Marimuthu, Steve Anderson, HunTeak Lee, HeeJo Chi
  • Patent number: 9362161
    Abstract: A semiconductor device has a plurality of semiconductor die. A substrate is provided with bumps disposed over the substrate. A first prefabricated insulating film is disposed between the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The bumps include a copper core encapsulated within copper plating. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The substrate includes a conductive layer formed in the substrate and coupled to the bumps. The semiconductor die is disposed between the bumps of the substrate. The bumps and the semiconductor die are embedded within the first prefabricated insulating film. A portion of the first prefabricated insulating film is removed to expose the bumps. The bumps electrically connect the substrate to the interconnect structure.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: June 7, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: HeeJo Chi, HanGil Shin, NamJu Cho
  • Patent number: 9355939
    Abstract: A method of manufacture of an integrated circuit package system includes: providing a base package substrate including: forming component contacts on a component side of the base package substrate, forming system contacts on a system side of the base package substrate, and forming a reference voltage circuit between the component contacts and the system contacts; mounting a first integrated circuit die on the component contacts; mounting a lead frame on the first integrated circuit die and coupled to the component contacts; and isolating a conductive shield from the lead frame, the conductive shield coupled to the reference voltage circuit.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: May 31, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: NamJu Cho, HeeJo Chi, HanGil Shin
  • Patent number: 9355983
    Abstract: A system and a method of manufacture thereof of integrated circuit packaging system, including: a pillar; a conductive buildup attached to the pillar; and a molded body encapsulating the conductive buildup, the pillar extending out of the molded body.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: May 31, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Bartholomew Liao Chung Foh, Dao Nguyen Phu Cuong, Jeffrey David Punzalan
  • Patent number: 9355993
    Abstract: A system and method of manufacture of an integrated circuit system includes: a die having a via, the die having a top side and a bottom side; a top interconnect mounted to the via at the top side; an interconnect pillar mounted to the via at the bottom side; a device interconnect mounted to the interconnect pillar; and a base adhesive covering the interconnect pillar and the device interconnect.
    Type: Grant
    Filed: July 3, 2015
    Date of Patent: May 31, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Won Kyoung Choi, Pandi Chelvam Marimuthu
  • Patent number: 9355962
    Abstract: A method of manufacture of an integrated circuit package stacking system including: forming a base frame includes: providing a support panel, and forming a coupling pad, a mounting pad, a base frame trace, a discrete component pad, or a combination thereof on the support panel; fabricating a package substrate; coupling an integrated circuit die to the package substrate; mounting the base frame over the integrated circuit die and the package substrate; and removing the support panel from the base frame.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: May 31, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: SeongMin Lee, Sungmin Song, Jong-Woo Ha
  • Publication number: 20160148882
    Abstract: A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground point. A plurality of semiconductor die is mounted to the substrate over the ground shield. The ground shield extends beyond a footprint of the plurality of semiconductor die. An encapsulant is formed over the plurality of semiconductor die and substrate. Dicing channels are formed in the encapsulant, between the plurality of semiconductor die, and over the ground shield. A plurality of metal-filled holes is formed along the dicing channels, and extends into the substrate and through the ground shield. A top shield is formed over the plurality of semiconductor die and electrically and mechanically connects to the ground shield through the metal-filled holes. The top and ground shields are configured to block electromagnetic interference generated with respect to an integrated passive device disposed in the semiconductor die.
    Type: Application
    Filed: January 29, 2016
    Publication date: May 26, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventors: OhHan Kim, SunMi Kim, KyungHoon Lee
  • Patent number: 9349666
    Abstract: An integrated circuit packaging system includes: providing a base substrate; applying a molded under-fill on the base substrate; forming a substrate contact extender through the molded under-fill and in direct contact with the base substrate; mounting a stack device over the molded under-fill; attaching a coupling connector from the substrate contact extender to the stack device; and forming a base encapsulation on the stack device, the substrate contact extender, and encapsulating the coupling connector.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: May 24, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: JoHyun Bae, In Sang Yoon, DaeSik Choi
  • Patent number: 9349616
    Abstract: A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. An insulating layer is formed over the encapsulant and a first surface of the semiconductor die. A semiconductor component is disposed over the insulating layer and first surface of the semiconductor die. A first interconnect structure is formed over the encapsulant and first surface of the semiconductor die to embed the semiconductor component. A conductive via is formed in the semiconductor die. A heat sink is formed over the semiconductor die. A second interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the semiconductor component. An opening is formed in the insulating layer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 24, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: KyungHoon Lee, HyunJin Song, Kyoungll Huh, DaeSik Choi