Abstract: An integrated circuit (IC) includes: a first functional analog pin or pad; a first analog test bus coupled to the first functional analog pin or pad; first and second analog circuits coupled to the first analog test bus; and a test controller configured to: when the IC is in a functional operating mode, connect an input or output of the first analog circuit to the first analog test bus so that the input or output of the first analog circuit is accessible by the first functional analog pin or pad, and keep disconnected an input or output of the second analog circuit from the first analog test bus, and when the IC is in a test mode, selectively connect the input or output of the first and second analog circuits to the first analog test bus to test the first and second analog circuits using the first analog test bus.

Abstract: A processor includes a synchronous circuit including a plurality of processing stages, wherein each processing stage includes a selection data bus; and an asynchronous circuit coupled to each selection data bus, wherein the asynchronous circuit includes an asynchronous state machine whose states correspond to a process phase or a plurality of circuits, wherein the asynchronous circuit further includes a selectable delay circuit whose delay is determined by a present state of the asynchronous state machine, and wherein the asynchronous circuit is configured for generating a plurality of processing stage clock signals each having a selectable delay provided by the selectable delay circuit.

Abstract: In an embodiment a system on chip includes at least one master device, at least one slave device, a connection interface configured to route signals between the at least one master device and the at least one slave device, the connection interface configured to operate according to configuration parameters, and a configuration bus connected to the connection interface, wherein the configuration bus is configured to deliver new configuration parameters to the connection interface so as to adapt operation of the connection interface.

Abstract: A method includes providing a reference clock signal having a reference period, providing a sampling clock signal having a sampling clock period shorter than the reference period of the reference clock signal, measuring the first subperiod as a first ratio of the first subperiod to the period of the sampling clock signal, measuring the second subperiod as a second ratio of the second subperiod to the period of the sampling clock signal, detecting a starting edge of a clock signal having a clock period greater than the reference period, producing a reconstructed reference signal based on the first ratio, the second ratio, and the detected starting edge, comparing the clock period of the clock signal with a period of the reconstructed reference signal to obtain a differential signal indicating a difference therebetween, and providing the differential signal to user circuitry for calibrating the clock signal.

Abstract: In start-up, current is sourced by a current source to a first plate of a first capacitor while a second capacitor is maintained at zero charge. In a subsequent first operating phase, current is sourced to a first plate of the second capacitor while a second plate of the first capacitor is connected to the first plate of the second capacitor. At the end of the first operating phase, the first capacitor is discharged. In a subsequent second operating phase, current is sourced to the first plate of the first capacitor while a second plate of the second capacitor is connected to the first plate of the first capacitor. At the end of the second operating phase, the second capacitor is discharged. Steady state operation of the circuit involves an alternation of the first and second operating phases interleaved with transition phases where the first and second capacitors are discharged.

Abstract: A converter circuit converts an input signal applied across a first and a second input node into a converted output signal across a first and a second output node. The converter circuit includes a switching network coupled to the first input node via an inductor having a current flowing therethrough. In a hysteresis current control mode of the switching network, the current flowing through the inductor has a triangular waveform with rising and falling edges between a first current threshold and a second current threshold alternating with a switching frequency. The switching frequency is controlled by varying the distance between the first current threshold and the second current threshold.

Abstract: In accordance with an embodiment, an ultrasound transmitter device includes a transformer comprising a secondary winding configured to be coupled to a piezoelectric transducer; a plurality of transistors coupled to the primary winding of the transformer and to a ground terminal via a sense resistor; an amplifier having an output coupled to control nodes of the plurality of transistors, a first input coupled to the sense resistor, and second input coupled to a reference resistor; a switching circuit configured to alternately couple control nodes of the plurality of transistors to an output of amplifier and to a reference node via complementary pulse signals, wherein the switching circuit is configured to turn on and turn off the plurality of transistors and operate the plurality of transistors in a push-pull manner; and a digital-to-analog converter having an output coupled to the reference resistor.

Abstract: A time based boost DC-DC converter generates an output voltage using an inductor. A voltage error between the output voltage and a reference voltage is determined and processed in a) an integral control branch which converts the voltage error into an integral control current signal used to control a current controlled oscillator, and b) a proportional branch which converts the voltage error into a proportional control current signal used to control signal a delay line. Current flowing in the inductor is sensed, attenuated and used to apply adjustment to the integral and proportional control current signals. The output from the current controlled oscillator is passed through the delay line and phase detected in order to generate pulse width modulation (PWM) control signaling driving switch operation in the converter.

Abstract: A leadframe has a die pad area and an outer layer of a first metal having a first oxidation potential. The leadframe is placed in contact with a solution containing a second metal having a second oxidation potential, the second oxidation potential being more negative than the first oxidation potential. Radiation energy is then applied to the die pad area of the leadframe contacted with the solution to cause a local increase in temperature of the leadframe. As a result of the temperature increase, a layer of said second metal is selectively provided at the die pad area of the leadframe by a galvanic displacement reaction. An oxidation of the outer layer of the leadframe is then performed to provide an enhancing layer which counters device package delamination.

Abstract: A semiconductor product includes a layer of semiconductor die package molding material embedding a semiconductor die having a front surface and an array of electrically-conductive bodies such as spheres or balls around the semiconductor die. The electrically-conductive bodies have front end portions around the front surface of the semiconductor die and back end portions protruding from the layer of semiconductor die package molding material. Electrically-conductive formations are provided between the front surface of the semiconductor die and front end portions of the electrically-conductive bodies left uncovered by the package molding material. Light-permeable sealing material can be provided at electrically-conductive formations to facilitate inspecting the electrically-conductive formations via visual inspection through the light-permeable sealing material.

Abstract: A power MOSFET driver circuit includes a feedback circuit configured to supply a feedback signal that signals when a gate voltage of the power MOSFET crosses a plateau value and the power MOSFET switches conduction state. The feedback circuit includes a comparator with a replica MOSFET of the power MOSFET, with scaled down dimensions, whose gate is coupled to the gate electrode of the power MOSFET. A bistable circuit has an input coupled to an output of the replica MOSFET and is configured to change a logic state of the feedback signal following the transition of the switching signal when the gate voltage of the power MOSFET crosses the plateau value and the power MOSFET switches conduction state.

Abstract: A processing system includes a communication system and a processing core configured to generate write requests. A circuit has associated a slave interface circuit configured to manage an address sub-range and selectively forward write requests addressed to a given address. Configuration data specifies whether the given address is protected/unprotected and locked/unlocked. In response to a received write request, address and data are extracted and a determination based on the configuration data is made as to whether the extracted address is protected/unprotected, and locked/unlocked. When the extracted address is unprotected or unlocked, the slave interface forwards the write request. When the extracted address is protected and locked, the slave interface generates an unlock signal in response to a comparison of the extracted address with the extracted data, with the unlock signal being asserted when the extracted data satisfy a predetermined rule with respect to the extracted address.

Abstract: A MEMS actuator includes a main body having a central portion, couplable to a substrate, and a peripheral portion suspended over the substrate when the central portion is coupled to the substrate. The peripheral portion has a deformable structure extending around the central portion, and forming successively arranged membranes. The MEMS actuator includes bearing structures and corresponding piezoelectric actuators. The bearing structures are fixed at their top to the deformable structure and laterally delimit corresponding cavities, each having a lateral opening facing the central portion of the main body and closed at the top by a membrane. A fixed part of the membrane is fixed to the underlying bearing structure and a suspended part is laterally offset with respect to the underlying bearing structure. The piezoelectric actuators are controllable to cause deformation of the corresponding membrane and rotation of the bearing structures around the central portion of the main body.

Abstract: A MEMS micromirror device is formed in a package including a containment body and a lid transparent to a light radiation. The package forms a cavity housing a tiltable platform having a reflecting surface. A metastructure is formed on the lid and/or on the reflecting surface and includes a plurality of diffractive optical elements.

Abstract: In an embodiment a circuit includes a voltage-controlled oscillator (VCO) circuit having a first node configured to receive a reference voltage, a second node configured to receive a feedback signal, which is a comparison signal, indicative of a variation of a regulated output voltage of an electronic voltage regulator with respect to the reference voltage and a third node configured to provide a clock signal having a clock period based on the reference voltage and the feedback signal, and a pulse-width modulated (PWM) signal generator circuit having a first node coupled to the VCO circuit and configured to receive the clock signal, a second node configured to receive an input signal proportional to an input voltage signal at an input node of the electronic voltage regulator and a third node configured to provide at least one PWM drive signal to one or more electronic switches of a switching stage based on the clock signal.

Abstract: A phase-change memory (PCM) includes a semiconductor body housing a selection transistor; a electrical-insulation body disposed over the semiconductor body; a conductive region, extending through the electrical-insulation body, electrically coupled to the selection transistor; and a plurality of heater elements in the electrical-insulation body. Each of the plurality of heater elements include a first end in electrical contact with a respective portion of the conductive region and a second end that extends away from the conductive region. The PCM further includes a plurality of phase-change elements extending in the electrical-insulation body and including data storage regions, where each of the data storage regions being electrically and thermally coupled to one respective heater element at the second end of the respective heater element.

Abstract: An inertial structure is elastically coupled through a first elastic structure to a supporting structure so as to move along a sensing axis as a function of a quantity to be detected. The inertial structure includes first and second inertial masses which are elastically coupled together by a second elastic structure to enable movement of the second inertial mass along the sensing axis. The first elastic structure has a lower elastic constant than the second elastic structure so that, in presence of the quantity to be detected, the inertial structure moves in a sensing direction until the first inertial mass stops against a stop structure and the second elastic mass can move further in the sensing direction. Once the quantity to be detected ends, the second inertial mass moves in a direction opposite to the sensing direction and detaches the first inertial mass from the stop structure.

Abstract: A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.

Abstract: Disclosed herein is an integrated component formed by a first wafer having first and second trenches defined in a top surface thereof, and a second wafer coupled to the first wafer and formed by a substrate with a structural layer thereon that integrated an electromagnetic radiation detector overlying the second trench. A first cap is coupled to the second wafer, overlies the electromagnetic radiation detector, and serves to define a first air-tight chamber in which the electromagnetic radiation detector is positioned. A stator, a rotor, and a mobile mass are integrated within the substrate and form a drive assembly for driving the mobile mass. The rotor overlies the first trench. A second cap is coupled to the second wafer, overlies the mobile mass, and serving to define a second air-tight chamber in which the mobile mass is positioned.

Abstract: A control circuit for controlling a switching stage of an electronic converter includes a first terminal configured to provide a drive signal and a second terminal configured to receive a first feedback signal. A third terminal receives a second feedback signal and a driver circuit provides the drive signal as a function of a PWM signal. A PWM signal generator circuit generates the PWM signal as a function of the first feedback signal, a reference threshold and the second feedback signal or a slope compensation signal. The control circuit is configured to sense an input signal, provide a first compensation parameter, and provide a first compensating signal as a function of a power of the input sensing signal.