Patents Assigned to STMicroelectron S.r.l.
  • Patent number: 12021454
    Abstract: A control circuit for a multiphase buck converter includes a regulator circuit and a plurality of phase control circuits. The regulator circuit generates a regulation signal based on a feedback signal and a reference signal, and each phase control circuit receives a current sense signal and generates a respective PWM signal based on the respective current sense signal and the regulation signal. The control circuit includes a first selector circuit and a second selector circuit configured to receive a selection signal and selectively connect each phase control circuit of a subset of the phase control circuits to a PWM signal for driving a respective stage of the multiphase buck converter, and to a current sense signal provided by the respective stage of the multiphase buck converter. A selection control circuit generates the selection signal in order to connect the phase control circuits to different stages of the multiphase buck converter.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: June 25, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Gerardo Castellano, Leonardo Pedone, Filippo Minnella, Marcello Raimondi
  • Patent number: 12017910
    Abstract: A first electronic component, such as a sensor having opposed first and second surfaces and a first thickness, is arranged on a support member with the second surface facing towards the support member. A second electronic component, such as an integrated circuit mounted on a substrate and having a second thickness less than the first thickness, is arranged on the support member with a substrate surface opposed the second electronic component facing towards the support member. A package molding material is molded onto the support member to encapsulate the second electronic component while leaving exposed the first surface of the first electronic component. The support member is then removed to expose the second surface of the first electronic component and the substrate surface of the substrate.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: June 25, 2024
    Assignees: STMicroelectronics (MALTA) Ltd, STMicroelectronics S.r.l.
    Inventors: Kevin Formosa, Marco Del Sarto
  • Patent number: 12021052
    Abstract: A semiconductor product includes a layer of semiconductor die package molding material embedding a semiconductor die having a front surface and an array of electrically-conductive bodies such as spheres or balls around the semiconductor die. The electrically-conductive bodies have front end portions around the front surface of the semiconductor die and back end portions protruding from the layer of semiconductor die package molding material. Electrically-conductive formations are provided between the front surface of the semiconductor die and front end portions of the electrically-conductive bodies left uncovered by the package molding material. Light-permeable sealing material can be provided at electrically-conductive formations to facilitate inspecting the electrically-conductive formations via visual inspection through the light-permeable sealing material.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: June 25, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventor: Fulvio Vittorio Fontana
  • Patent number: 12015515
    Abstract: A transmitter circuit receives a PWM input signal and a clock signal. A logic circuit generates a control signal as a function of the clock signal. The control signal is normally set to high, and is periodically set to low for a transmission time interval when an edge is detected in the clock signal. The transmission time interval is shorter than a half clock period of the clock signal. A tri-state transmitter receives the PWM input signal and the control signal, and produces first and a second output signals at first and second transmitter output nodes, respectively. The output signals have a voltage swing between a positive voltage and a reference voltage. An output control circuit is sensitive to the control signal and is coupled to the first and second transmitter output nodes.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: June 18, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Valerio Bendotti, Nicola De Campo, Carlo Curina
  • Patent number: 12011269
    Abstract: In an embodiment, a method of processing an electrophysiological signal includes collecting the electrophysiological signal that is indicative of a level of attention of a human; filtering the electrophysiological signal via joint low-pass and high-pass filtering using a set of filtering parameters including low-pass filters parameters and high-pass filters parameters having a set of low-pass cut-off frequencies and a set of high-pass cut-off frequencies respectively. The method further includes applying artificial neural network processing to the filtered electrophysiological signal to extract therefrom a set of features of the electrophysiological signal. The method further includes applying classifier processing to the set of features extracted from the filtered electrophysiological signal and producing a classification signal indicative of the level of attention of the human. The method further includes generating a trigger signal to trigger a user circuit based on the classification signal.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: June 18, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Francesco Rundo, Sabrina Conoci
  • Patent number: 12015346
    Abstract: A DC-DC boost converter includes an inductor coupled between an input voltage and an input node, a diode coupled between the input node and an output node, and an output capacitor coupled between the output node and ground such that an output voltage is formed across the output capacitor. A switch selectively couples the input node to ground in response to a drive signal. Control loop circuitry includes an error amplifier to generate an analog error voltage based upon a comparison of a feedback voltage to a reference voltage, the feedback voltage being indicative of the output voltage, a quantizer to quantize the analog error voltage to produce a digital error signal, and a drive voltage generation circuit to generate the drive signal as having a duty cycle based upon the digital error signal.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: June 18, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Andrea Barbieri, Aldo Vidoni, Marco Zamprogno
  • Patent number: 12009743
    Abstract: A method of operating an electronic converter is provided in which a switching activity of a switching stage of the electronic converter is active or inactive based on a control signal, and the method includes operating the electronic converter, alternatively, in a first or a second mode. In the first mode, the status signal is initially asserted and is de-asserted in response to an amplitude of the input sensing signal failing to reach a first reference threshold value. In the second mode, the status signal is initially de-asserted and an auxiliary power supply signal is periodically varied with a variation period. After a time interval equal to the variation period, a comparison signal is asserted in response to an amplitude of the sensed signal reaching a second reference threshold value. The status signal is asserted based on conditions of the comparison signal and the periodically varying auxiliary power supply signal.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: June 11, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Christian Leone Santoro, Domenico Tripodi
  • Patent number: 12007521
    Abstract: A detection method of a user of an apparatus is provided in which the apparatus is coupled to a charge variation sensor having a control unit and an electrode to detect an electric/electrostatic charge variation of the user. The detection method includes acquiring, through the electrode, a charge variation signal indicative of the presence of the user. A filtered signal is generated by filtering the charge variation signal. A feature signal is generated as a function of the filtered signal. A movement signal indicative of a movement of the user is generated as a function of the feature signal. A presence signal indicative of the presence of the user is generated as a function of the movement signal.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: June 11, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Federico Rizzardini, Lorenzo Bracco
  • Publication number: 20240186198
    Abstract: A semiconductor chip or die is mounted at a position on a support substrate. A light-permeable laser direct structuring (LDS) material is then molded onto the semiconductor chip positioned on the support substrate. The semiconductor chip is visible through the LDS material. Laser beam energy is directed to selected spatial locations of the LDS material to structure in the LDS material a pattern of structured formations corresponding to the locations of conductive lines and vias for making electrical connection to the semiconductor chip. The spatial locations of the LDS material to which laser beam energy is directed are selected as a function of the position the semiconductor chip which is visible through the LDS material, thus countering undesired effects of positioning offset of the chip on the substrate.
    Type: Application
    Filed: February 9, 2024
    Publication date: June 6, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventors: Pierangelo MAGNI, Michele DERAI
  • Patent number: 12003177
    Abstract: A switching regulator circuit has a high side (HS) transistor actuated during on time (TON) of a duty cycle. The output current of the switching regulator circuit is determined from sensing a transistor current flowing through the HS transistor during HS transistor on time (TON) and dividing the sensed transistor current by the duty cycle to generate an output signal indicative of the output current of the switching regulator circuit. The duty cycle is determined from a ratio of the on time (TON) and off time (TOFF) of the switching regulator circuit.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: June 4, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco La Pila, Giuseppe Platania
  • Patent number: 12001012
    Abstract: Disclosed herein is a microelectromechanical (MEMS) device, including a rotor and a first piezoelectric actuator mechanically coupled to the rotor. The first piezoelectric actuator is electrically coupled between a first signal node and a common voltage node. A second piezoelectric actuator is mechanically coupled to the rotor, and is electrically coupled between a second signal node and the common voltage node. Control circuitry includes a drive circuit configured to drive the first and second piezoelectric actuators, a sense circuit configured to process sense signals generated by the first and second pizeoelectric actuators, and a multiplexing circuit. The multiplexing circuit is configured to alternate between connecting the drive circuit to the first piezoelectric actuator while connecting the sense circuit to the second piezoelectric actuator, and connecting the drive circuit to the second piezoelectric actuator while connecting the sense circuit to the first piezoelectric actuator.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: June 4, 2024
    Assignees: STMicroelectronics S.r.l., STMicroelectronics Ltd
    Inventors: Davide Terzi, Gianluca Mendicino, Dadi Sharon
  • Patent number: 12003247
    Abstract: A signal processing circuit includes a filter generating a quantizer input signal from a noise shaping input signal and a quantizer output signal. A quantizer divides the quantizer input signal by a scaling factor to produce a noise shaping output signal and multiplies the noise shaping output signal by the scaling factor to produce the quantizer output signal. Receiver circuitry scales the quantizer output signal by a second scaling factor. A dynamic range optimization circuit compares a current value of the noise shaping input signal to a threshold value, lowers or raises the scaling factor in response to the comparison, and proportionally lowers or raises the scaling factor such that a ratio between the scaling factor and second scaling factor remains substantially constant.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: June 4, 2024
    Assignee: STMicroelectron S.r.l.
    Inventor: Francesco Stilgenbauer
  • Publication number: 20240176586
    Abstract: An IMC circuit includes a memory cells arranged in matrix. Computational weights for an IMC operation are stored in groups of cells. Each row of groups of cells includes a positive and negative word linen. Each column of groups of cells includes a bit line. The IMC operation includes a first elaboration where a word line signal is applied to the positive/negative word line of the group of cells depending on the positive/negative sign, respectively, of the coefficient data, with a positive MAC output on the bit line. In a second elaboration, a word line signal is applied to the negative/positive word line of the group of cells depending on the positive/negative sign, respectively, of the coefficient data, with a negative MAC output on the bit line. The IMC operation result is obtained from a difference between the positive and negative MAC operations.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventors: Marcella CARISSIMI, Paolo Sergio ZAMBOTTI, Riccardo ZURLA
  • Publication number: 20240178054
    Abstract: A body of semiconductor material has a surface and accommodates an active area, conductive regions, a first deep insulation structure extending in the active area from the surface of the body in a first trench, and a second deep insulation structure extending in the active area from the surface of the body in a second trench and surrounding the conductive regions. The first deep insulation structure has insulation walls surrounding a conductive filling portion. The second deep insulation structure has a solid insulating region filling the second trench. The first deep insulation region has a first width and a first depth and the second deep insulation structure has a second width and a second depth. The second width is smaller than the first width and the second depth is smaller than the first depth.
    Type: Application
    Filed: November 28, 2023
    Publication date: May 30, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventors: Emanuele LAGO, Nunzia MALAGNINO, Damiano RICCARDI
  • Patent number: 11996851
    Abstract: A circuit for decoding a pulse width modulated (PWM) signal generates an output signal switching between a first and second logic values as a function of a duty-cycle of the PWM signal. Current generating circuitry receives the PWM signal and injects a current to and sinks a current from an intermediate node as a function of the values of the PWM signal. A capacitor coupled to the intermediate node is alternatively charged and discharged by the injected and sunk currents, respectively, to generate a voltage. A comparator circuit coupled to the intermediate node compares the generated voltage to a comparison voltage and drives the logic values of the output signal as a function of the comparison.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: May 28, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Vanni Poletto, Ivan Floriani
  • Patent number: 11995333
    Abstract: A method of managing an integrated circuit memory includes identifying a set of allocated regions and a set of empty regions spanning a memory space of an integrated circuit card, selecting the biggest empty region of the set of empty regions, determining that an allocated memory block of an allocated region immediately adjacent to the biggest empty region is larger than the biggest remaining empty region of the memory space, storing the allocated memory block in a temporary list of skipped memory blocks, removing the allocated memory block from the set of allocated memory regions, and swapping the allocated memory block with a remaining empty region to widen the biggest empty region.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: May 28, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventor: Francesco Caserta
  • Patent number: 11996158
    Abstract: A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.
    Type: Grant
    Filed: July 10, 2023
    Date of Patent: May 28, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giampiero Borgonovo, Lorenzo Re Fiorentin
  • Patent number: 11990829
    Abstract: A configurable voltage regulating circuit includes first through fourth switches. A flying capacitor is coupled between a common mode node and a pump node, and a sense resistance network is coupled between an output node and an input of an error amplifier and configured to provide a sensed output voltage. The error amplifier receives at another input a reference voltage and generates an error signal. A charging circuit supplies a charging current to the pump node, and controls the value of the charging current as a function of the error signal. A switch command signals generator generates respective first, second, third, and fourth switch signals to control the first switch, second switch, third switch, and fourth switch. The generator sets the configurable voltage regulating circuit as either a charge pump or a linear regulator based the input voltage being less than a first threshold or greater than a second threshold.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: May 21, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Matteo Venturelli, Nicola De Campo
  • Patent number: 11990442
    Abstract: A semiconductor die is mounted at a die area of a ball grid array package that includes an array of electrically-conductive ball. A power channel conveys a power supply current to the semiconductor die. The power channel is formed by an electrically-conductive connection plane layers extending in a longitudinal direction between a distal end at a periphery of the package and a proximal end at the die area. A distribution of said electrically-conductive balls is made along the longitudinal direction. The electrically-conductive connection plane layer includes subsequent portions in the longitudinal direction between adjacent electrically-conductive balls of the distribution. Respective electrical resistance values of the subsequent portions monotonously decrease from the distal end to the proximal end. A uniform distribution of power supply current over the length of the power channel is thus facilitated.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: May 21, 2024
    Assignee: STMicroelectron S.r.l.
    Inventors: Cristina Somma, Aurora Sanna, Damian Halicki
  • Patent number: 11982928
    Abstract: A scanning laser projector includes an optical module with a housing defined by a top surface, a bottom surface, and sidewalls extending between the top surface and bottom surface to define an interior compartment within the housing. A given one of the sidewalls has an exit window defined therein. A first light detector is positioned at an interior surface of the given one of the sidewalls about a periphery of the exit window. A second light detector positioned at the interior surface of the given one of the sidewalls about the periphery of the exit window and on a different side thereof than the first light detector.
    Type: Grant
    Filed: November 2, 2022
    Date of Patent: May 14, 2024
    Assignees: STMicroelectronics LTD, STMicroelectronics S.r.l.
    Inventors: Alex Domnits, Elan Roth, Davide Terzi, Luca Molinari, Marco Boschi