Abstract: A variable gain amplifier having an input node, a variable current source including a control input coupled to the input node, first and second branches coupled in parallel between a first supply terminal and the variable current source, the first and second branches defining a differential pair arranged to be controlled by first and second differential gain signals and having first and second output terminals, one of the output terminals including an output node of the variable gain amplifier; and a potential divider having a middle node coupled to the first and second output terminals, wherein the middle node is also coupled to the input node by a capacitor.
Abstract: A method for monitoring the execution of a program by a processor of an electronic circuit comprises operations of collecting monitoring data within the circuit and of transmitting the monitoring data to a device for debugging the program. The monitoring data are transmitted via a connection external to the circuit, comprising at least one serial connection. The monitoring data are serialized within the circuit before being transmitted, then restored within the device for tuning the program.
Abstract: A power supply circuit and a transponder having a circuit for rectifying an A.C. voltage and two power storage elements, the rectifying circuit providing a rectified voltage to at least one of the storage elements and an output voltage being provided by at least one of the storage elements, and at least one switching element for switching the circuit operation between a state of provision of a relatively high voltage and a state of provision of a relatively low voltage, the second state configuring the rectifying circuit in halfwave operation.
Abstract: A semiconductor structure including a first active area under which is buried a first reflective layer and a least one second active area under which is buried a second reflective layer, wherein the upper surface of the second reflective layer is closer to the upper surface of the structure than the upper surface of the first reflective layer.
Type:
Application
Filed:
March 5, 2009
Publication date:
October 15, 2009
Applicant:
STMicroelectronics S.A.
Inventors:
Perceval Coudrain, Philippe Coronel, Michel Marty, Matthieu Bopp
Abstract: A terminal for generating an electromagnetic field, including an oscillating circuit capable of receiving a high-frequency A.C. excitation voltage via an amplifier and a directional coupler, the oscillating circuit having at least one element of variable capacitance, and circuitry for modifying the value of this capacitance according to the amplitude of a signal extracted from the coupler.
Abstract: A region is locally modified so as to create a zone that extends as far as at least part of the surface of the region and is formed from a material that can be removed selectively with respect to the material of the region. The region is then covered with an insulating material. An orifice is formed in the insulating material emerging at the surface of the zone. The selectively removable material is removed from the zone through the orifice so as to form a cavity in place of the zone. The cavity and the orifice are then filled with at least one electrically conducting material so as to form a contact pad.
Abstract: A binary frequency divider includes a counter paced by an input signal, means for comparing a counting value with first and second threshold values and supplying first and second control signals synchronized with variation edges of a first type of the input signal. The divider includes means for supplying at least one third control signal shifted by a half-period of the input signal in relation to one of the first or second control signals, and control means for generating the output signal using control signals chosen according to the value of at least one least significant bit of the division setpoint. Application is mainly but not exclusively to UHF transponders.
Type:
Grant
Filed:
June 18, 2008
Date of Patent:
October 13, 2009
Assignee:
STMicroelectronics S.A.
Inventors:
Christophe Moreaux, Ahmed Kari, David Naura, Pierre Rizzo
Abstract: A metal barrier is realized on top of a metal portion of a semiconductor product, by forming a metal layer on the surface of the metal portion, with this metal layer comprising a cobalt-based metal material. Then, after an optional deoxidation step, a silicidation step and a nitridation step of the cobalt-based metal material of the metal layer are performed. The antidiffusion properties of copper atoms (for example) and the antioxidation properties of the metal barrier are improved.
Type:
Grant
Filed:
October 12, 2007
Date of Patent:
October 13, 2009
Assignee:
STMicroelectronics S.A.
Inventors:
Laurin Dumas, Cécile Jenny, Pierre Caubet
Abstract: Embodiments of the invention concern a method for transmitting digital messages through a microprocessor monitoring circuit of specific type and integrated to a microprocessor, each message including an identifier and consisting of several groups of successive and juxtaposed bits divided into segments. The method consists in successively transmitting segments associated with a first group corresponding to the identifier and comprising a fixed number of bits; with second groups, at least one of the second group comprising a fixed number of bits depending on the type of monitoring circuit, the number of other second groups being independent of the type of monitoring circuit; with a third group comprising a number of bits greater than one; and with fourth groups comprising each a number of bits greater than one, the number of fourth groups depending on the identifier and on the type of monitoring circuit.
Abstract: The integrated circuit includes a memory device of the irreversibly electrically programmable type. This device includes several memory cells, each memory cell having a dielectric zone positioned between a first electrode and a second electrode. Each memory cell is further associated with an access transistor. At least one first electrically conductive link electrically couples to the first electrodes of at least two memory cells, these first two electrodes being coupled to one and the same bias voltage. The first electrically conductive link is positioned in substantially a same plane as the first electrodes of the two memory cells.
Type:
Application
Filed:
April 7, 2009
Publication date:
October 8, 2009
Applicant:
STMicroelectronics S.A.
Inventors:
Philippe Candelier, Philippe Gendrier, Joel Damiens, Elise Le Roux
Abstract: A memory device of the irreversibly electrically programmable type is provided with a memory cell having a dielectric zone disposed between a first electrode and second electrode. An access transistor is connected in series with the second electrode, and an auxiliary transistor is connected in series with the first electrode. The auxiliary transistor is biased to have a saturation current which is lower than a saturation current of the access transistor when both the auxiliary and access transistors are actuated. A number of the memory cells are arranged in a memory plane to form the memory device.
Abstract: A programmable control interface is for circuits using complex commands. The programmable interface includes a memory for storing sampled commands and a sequencing circuit. The sequencing circuit is programmable. Thus, a processor downloads into the programmable interface a sequencing specific to the sequence of commands. Once the programmable interface has been programmed, the processor launches the start of the sequence and the programmable interface manages and controls in a standalone manner the inputs/outputs with the slave circuit. The management and control of the slave circuit is independent of any interrupt specific to the system. The programmable interface uses a software-type upgrade to interface with new slave circuits that may appear on the market.
Abstract: A channel equalizer having a filter arranged to filter an input signal, the filter including a plurality of taps, each tap generating an output signal based on a coefficient, an input for receiving the coefficients and an output for outputting a filtered signal; and coefficient generating circuitry including a graduation unit arranged to receive the input signal and an error signal indicating an error in the filtered signal, to accumulate gradient values relating to each of the coefficients based on a plurality of error values of the error signal, each of the gradient values indicating a required change in one of the coefficients, and to sequentially output the gradient values; and coefficient update unit arranged to sequentially update each of the filter coefficients in turn, based on the gradient values.
Abstract: An image sensor having a surface intended to be illuminated and pixels, each pixel including a photosensitive area formed in an active area of the substrate, at least one first pixel including a first microlens located on the surface, the sensor including at least one second pixel including a transparent portion forming a pedestal located at least partly on the surface and a second microlens at least partially covering the pedestal.
Abstract: A channel equalizer arranged to receive a data signal encoded by a plurality of amplitude levels, the circuitry including a filter having a plurality of taps, each tap generating an output signal based on a coefficient, an input for receiving an error signal for adapting the coefficients, and an output for outputting a filtered signal; and blind error generation circuitry arranged to generate the error signal, the blind error generation circuitry including: error estimating circuitry arranged to estimate the error of the filtered signal based on maximum likelihood; and adding circuitry coupled to the error estimating circuitry and to the output of the filter and arranged to add at least part of the filtered signal to the error estimated by the error estimating circuitry to generate the error signal.
Abstract: A current mirror includes at least a first and a second mirror transistors inserted between a first and a second voltage reference and connected to an input terminal and to an output terminal of the current mirror, respectively. The current mirror further includes a base current compensation block inserted between the input terminal and common control terminals of the first and second mirror transistors and connected to a voltage reference. The base current compensation block at least includes a bias current generator of a bias current and a first compensation transistor inserted, in series to each other, between the voltage reference and the input terminal, and a second compensation transistor inserted between the voltage reference and the common control terminals of the mirror transistors and having a control terminal connected to a control terminal of the first compensation transistor.
Abstract: A system for detecting the time exceeding conditions of at least one application being executed by a processor, including: an element for storing time conditions, the conditions being sorted by increasing deadline order; a register for storing the condition closest to the current date; and a comparator of the deadline contained in the register with the current date of the system.
Abstract: A method for protecting an integrated circuit, including at least one non-volatile memory, including the steps of detecting a possible disturbance in the flow of a program executed by the integrated circuit, modifying the value of a digital variable in a volatile storage element in case of a disturbance detection and, in a way independent in time from the detection, intervening upon the non-volatile memory according to the value of said variable.
Abstract: A digital processing unit for executing program instructions stored in at least two memories and including at least one first register of temporary storage of the operator of a current instruction to be executed and at least a second register of temporary storage of at least one argument or operand of said current instruction, and a protection circuit for submitting, upstream of the register, the operator to a deciphering function if this operator originates from one of the memories or from an area of these memories, identified from the address provided by a program counter. The present invention also relates to a method for protecting a program for updating an electronic circuit and controlling its execution, including at least one step of ciphering or deciphering of program instruction operators.
Abstract: An antenna switch module between several radio-frequency transmit and/or receive paths including, between a common terminal on the antenna side and an access capacitor specific to each path, at least one diode, the number of diodes directly connected to the common terminal being odd and the number of diodes having their cathode on the common terminal side being equal, with a difference of one, to the number of diodes having their anode on the common terminal side.