Abstract: A method of transferring guard values and a computer system, such as a processor for digital signal processing, including a parallel set of execution units that utilizes the method. A master set of guard indicators is held in association with one of the execution units. If other execution units require the guard values for particular guard indicators, a sendguard instruction is issued to the execution unit holding the master guard values. The sendguard instructions are held in a separate queue from the main instructions intended for that execution unit. Circuitry is provided in the execution unit to avoid stalling in the dispatch of sendguard instructions even in the context of earlier guard modifying instructions.

Abstract: The invention concerns a method for transmitting digital messages through output terminals (22) of a monitoring circuit (18) incorporated in a microprocessor (12) during execution of a series of instructions, the digital messages representing characteristic data stored by the monitoring circuit upon detecting a specific event in the execution of the series of instructions, one of said data corresponding to an identifier of said specific event, said method comprising the following steps: comparing the data of the last two detected specific events having a common identifier, if the compared data are identical, incrementing a repeat counter associated with said specific event; and if the compared data are different, transmitting a digital message representing the data of the last detected specific event, and furthermore, if the content of the repeat counter associated with said specific event is other than zero, transmitting a digital message indicating a repeat of the specific event.

Abstract: A light sensor located above an integrated circuit including a lower electrode, a heavily-doped amorphous silicon layer of a first conductivity type, and a lightly-doped amorphous silicon layer of a second conductivity type. The lightly-doped amorphous silicon layer rests on a planar surface at least above and in the vicinity of the lower electrode.

Abstract: The present invention relates to a method for programming or erasing memory cells that include a selection transistor connected to a floating-gate transistor. According to the method, a non-zero compensation voltage is applied to the gate of a transistor not involved in the programming or erasing process so as to increase a breakdown threshold of the transistor, and an inhibition voltage is applied to the gate or to a terminal of at least one floating-gate transistor connected to the transistor having its breakdown threshold increased to inhibit a phenomenon of soft programming or soft erase of the floating-gate transistor.

Abstract: A tunable filter circuit having inputs IN1-IN2 and outputs OUT1-OUT2, comprising at least a primary four-pole circuit including in cascade: a first varactor having a first electrode connected to IN1 and a second electrode; a first inductive resistor connected between the second electrode of the varactor and input IN2, a secondary four-pole circuit comprising four BAW resonators. First and second of these resonators have a first electrode connected to a first input of the secondary four-pole circuit and a second electrode connected to first and second outputs of the secondary four-pole circuit, respectively. Similarly, third and fourth of these resonators have a first electrode connected to a second input of the secondary four-pole circuit and a second electrode connected to the second and first outputs of the secondary four-pole circuit, respectively.

Abstract: A method and a circuit for ciphering or deciphering data with a key by using at least one variable stored in a storage element and updated by the successive operations, the variable being masked by at least one first random mask applied before use of the key, then unmasked by at least one second mask applied after use of the key, at least one of the masks being dividable into several portions successively applied to the variable and which, when combined, represent the other mask.

Abstract: A DRAM and its application to a mobile telephony circuit with a control circuit including a first refreshment controller controlled by a first clock signal and a second refreshment controller controlled by a second clock signal having a frequency less than that of the first one and used to synchronize events of the GSM network.

Abstract: An inductance formed in a stack of insulating layers, the inductance comprising first and second access terminals and first and second half-loops distributed in the stack of insulating layers on a number of distinct levels greater than or equal to four. For each level, each first half-loop is at least partly symmetrical to one of the second half-loops. All the first half-loops are series-connected according to a first succession of first half-loops to form first loops between the first access terminal and a midpoint and all the second half-loops are series-connected according to a second succession of second half-loops to form second loops between the second output terminal and the midpoint.

Abstract: A method for acquiring images using at least one CMOS-type sensor with four transistors including an acquisition node and a read node, where the read node can receive a compression signal, including a step of reading a reference state of the sensor; a reset step; an integration step, during which the sensor is exposed and during part of which the compression signal is applied to the read node; and a step of reading the data acquired during the integration step; the read node being, during the integration step, isolated from the acquisition node, except immediately before the application of the compression signal, at which time the acquisition node is connected to the read node long enough to enable a transfer of the charges present at the acquisition node to the read node.

Abstract: A device for reading from and/or writing on a rotating disk including a mobile opto-electromechanical device placed above the disk and connected to a motherboard via a set of electric wires. The opto-electromechanical device includes actuators, a laser diode, photodetectors, and an electronic circuit, each photodetector providing the electronic circuit with an analog electric signal proportional to the received light signal, the electronic circuit controlling the diode and the actuators. The electronic circuit comprises an analog-to-digital converter digitizing the analog electric signals coming from the photodetectors and transmitting the digitized signals to a digital processing unit providing data of alignment of the opto-electromechanical device with respect to the disk, and a reference clock signal having its period substantially corresponding to a multiple or to a sub-multiple of the time period corresponding to the overflight by the opto-electromechanical device of a bit of the disk.

Abstract: A binary frequency divider includes a counter paced by an input signal, means for comparing a counting value with first and second threshold values and supplying first and second control signals synchronized with variation edges of a first type of the input signal. The divider includes means for supplying at least one third control signal shifted by a half-period of the input signal in relation to one of the first or second control signals, and control means for generating the output signal using control signals chosen according to the value of at least one least significant bit of the division setpoint. Application is mainly but not exclusively to UHF transponders.

Abstract: A system is provided for modeling an integrated circuit including at least one insulated-gate field-effect transistor. The system includes generator means for defining a parameter representing mechanical stresses applied to the active area of the transistor, and processing means for determining at least one of the electrical parameters of the transistor based at least partially on the stress parameter. Also provided is a method of modeling an integrated circuit including at least one insulated-gate field-effect transistor, and a method of producing an integrated circuit including at least one insulated-gate field-effect transistor.

Abstract: A circuit for controlling the power in a load supplied by an A.C. voltage and directly connected to a first terminal of application of the A.C. voltage, including two isolated-gate bipolar transistors, connected in anti-parallel between a second terminal of application of the A.C. voltage and the load; circuitry for detecting the zero crossing of the A.C. supply voltage in a first direction; circuitry for generating, at each period of the supply voltage, a pulse of predetermined duration for controlling a first one of said transistors, the time of occurrence of the pulse being conditioned by the detection of the zero crossing of the A.C. voltage and by a desired power reference setting a variable delay of occurrence of the pulse with respect to the detected zero crossing; and circuitry for inverting and transferring said pulse to the second transistor.

Abstract: A capacitor fabricated, within an integrated circuit, has at least two capacitive trenches extending within a dielectric material. A metal layer is produced which is embedded in the dielectric material. To form the capacitor, the dielectric material is etched, with etching stopped at the metal layer so as to form the trenches. A layer of conductive material forming the lower electrode of the capacitor is then deposited at least on the sidewalls of the trenches and in contact with the metal layer. A dielectric layer is then deposited within the trenches. A layer of conductive material forming the upper electrode of the capacitor is then deposited within the trenches.

Abstract: The storage of values of a range block and of seven isometries used in a fractal image compression method, comprising using four memory areas of identical sizes in which are respectively stored the identity, and three first isometries corresponding to the isometries of symmetry with respect to the vertical axis, of 270° rotation, and of 90° rotation.

Abstract: An integrated circuit semiconductor substrate includes an active silicon layer separated from a silicon substrate layer by a buried insulating material layer. The active silicon layer, however, locally includes at least one over-thickness on the side of the buried layer, while maintaining a flat surface state of the semiconductor layer across the integrated circuit. The over-thickness is created by forming a cavity under the active silicon layer in the local area, and then providing the over-thickness by partially filling the cavity at the bottom of the active silicon layer through epitaxial growth. An insulating layer then fills the remaining portions of the cavity.

Abstract: An electronic circuit, including: a logic circuit having a plurality of logic cells; storage cells able to form a shift register, able to be connected to the logic cells; a connection control module having an input for the reception of an identification key, the module connecting the storage cells so as to form a test shift register when the receive input receives a valid identification key, and the module connecting the storage cells so as to form randomly a diversion circuit when the input does not receive a valid identification key. The invention allows the electronic circuit to be protected against fraudulent access in read or write mode. The invention also relates to a smart card including this electronic circuit.

Abstract: An electrical device includes two supports for electronic components. A first support bears at least one input terminal, an electric circuit connected to the input terminal and a voltage limiter. A second support bears at least one external connection terminal. The external connection terminal is connected to the input terminal by a capacitor, and the link between the capacitor and the external connection terminal includes a node connected to the voltage limiter device so as to limit a voltage between said node and a reference point of the electric circuit.

Abstract: A method for forming, by dry etch, an opening of a given shape in a silica glass layer, the layer having a doping profile similar to the shape and the etch plasma being a non-carbonated fluorinated plasma causing a non-directional etching.

Abstract: An integrated circuit includes at least one photosensitive element capable of delivering an electrical signal when light of at least one wavelength of the visible spectrum reaches it, and an electrooptic system functioning as an electrochemical shutter. The electrooptic system is located in the path of at least one light ray capable of reaching the photosensitive element and possesses at least one optical property, dependent on electrochemical reaction, that can be modified by an electrical control signal. The optical property is preferably transmission.