Abstract: An image sensor pixel structure including a photosensitive area; a stacking of insulating layers covering the photosensitive area; and a device for focusing the light of the pixel to the photosensitive area. The focusing device includes first and second microlenses, the first microlens being arranged between layers of the stacking and substantially conjugating the second microlens with the photosensitive area.
Abstract: A multivibrator circuit includes a first data transfer port that receives, as input, multivibrator input data, a first, master, latch cell connected on the output side of the first transfer port, a second, slave, latch cell, and a second data transfer port placed between the first and second latch cells, each latch cell comprising a set of redundant data storage nodes. The transfer ports each include circuitry for writing data separately into each storage node.
Abstract: A one-time programmable circuit uses forced BJT hFE degradation to permanently store digital information as a logic zero or logic one state. The forced degradation is accomplished by applying a voltage or current to the BJT for a specific time to the reversed biased base-emitter junction, allowing a significant degradation of the junction without destroying it.
Abstract: A process for depositing a silicon-based material on a substrate uses the technology of plasma-enhanced atomic layer deposition. The process is carried out over several cycles, wherein each cycle includes: exposing the substrate to a first precursor, which is an organometallic silicon precursor; and applying a plasma of at least a second precursor, different from the first precursor. Semiconductor products such as 3D capacitors, vertical transistor gate spacers, and conformal transistor stressors are made from the process.
Type:
Application
Filed:
April 24, 2007
Publication date:
November 1, 2007
Applicant:
STMicroelectronics S.A.
Inventors:
Michael Gros-Jean, Daniel Benoit, Jorge Regolini
Abstract: Silicon-based single-crystal portions are produced on a surface of a substrate, selectively in zones where a single-crystal material is initially exposed. To do this, a layer is firstly formed over the entire surface of the substrate, using a silicon precursor of the non-chlorinated hydride type, and under suitable conditions so that the layer is a single-crystal layer in the zones of the substrate where a single-crystal material is initially exposed and amorphous outside these zones. The amorphous portions of the layer are then selectively etched so that only the single-crystal portions of the layer remain on the substrate.
Abstract: A silicon-based single-crystal portion is produced on a substrate selectively in a zone where a single-crystal material is initially exposed. The portion is produced outside other surface zones where the surface of the substrate is made of insulating material. The single-crystal portion is formed from a gas mixture including a silicon precursor of the non-chlorinated hydride type, hydrogen chloride and a carrier gas. The process makes it possible to reduce the temperature at which the substrate has to be heated in order to form the single-crystal portion by selective epitaxial growth.
Abstract: A display screen is controlled through successive scans of the display screen. Each scan of the display screen includes a successive selection of rows of the display screen. For each row selected, and in accordance with a normal selection, a first column selection mode is implemented wherein a first selection signal is generated for the column, that first selection signal going from a first state towards a second state with an intermediate plateau level therebetween. In an alternative operation, a second column selection mode is provided which replaces the first column selection mode, the second column selection mode including the generation of a second selection signal going from the first state to the second state without any intermediate plateau level. At least at the start of each scan, the first selection mode is replaced by the second selection mode and this second selection mode is maintained for a given column, at the latest, for as long as no deselection of the column has been effected.
Abstract: In an integrated circuit, a diode is interposed between the semiconductor substrate and the contact pad to an external bias voltage, and the substrate is biased at an internal voltage reference. Between each contact pad of the integrated circuit and semiconductor substrate, there is positioned a protection device against permanent overloads and a protection device against electrostatic discharges. By isolating the semiconductor substrate from the external voltages source and by placing a protection device between each contact pad and the substrate, a broad, general protection of the integrated circuit is obtained against all the destructive phenomena such as overloads, positive and negative overvoltages, polarity reversal and electrostatic discharges.
Abstract: The present invention relates to a memory on a silicon microchip, having a serial input/output, an integrated memory array addressable under N bits, and at least one register that is read accessible, after applying a command for reading the register to the memory. The memory stores a most significant address allocated to the memory within an extended memory array wherein the memory is incorporated or intended to be incorporated. A master memory signal is generated based on the most significant address allocated to the memory. A central processing unit executes a command for reading the register and supplies the content of the register to the serial input/output of the memory only if the memory is the master memory within the extended memory array. The memory includes slave memories whose operation depends upon the read/write status of the master memory.
Type:
Grant
Filed:
December 9, 2004
Date of Patent:
October 30, 2007
Assignee:
STMicroelectronics S.A.
Inventors:
Sebastien Zink, Paola Cavaleri, Bruno Leconte
Abstract: For instruction clusters for which no significant performance penalty is incurred, such as execution of hardware loops, a processor automatically and dynamically switches to a pipelined two-cycle access to an associated associative cache rather than a single-cycle access. An access involving more than one cycle uses less power because only the hit way within the cache memory is accessed rather than all ways within the indexed cache line. To maintain performance, the single-cycle cache access is utilized in all remaining instructions. In addition, where instruction clusters within a hardware loop fit entirely within a pre-fetch buffer, the cache sub-system is idled for any remaining iterations of the hardware loop to further reduce power consumption.
Abstract: A window comparator of an A.C. input voltage, including, between two terminals of application of a voltage representative of the voltage to be measured, two first transistors of a first type, each first transistor being assembled as a current mirror on the second transistor having a first conduction terminal connected to one of the application terminals, the two second transistors having a second common conduction terminal; and two third transistors of a second type assembled as a current mirror between the common conduction terminal of the second transistors and a current source, a D.C. voltage being applied on a first terminal of the current source and an output signal being provided by a second terminal of the current source.
Abstract: The invention relates to a single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism
Type:
Application
Filed:
December 16, 2004
Publication date:
October 25, 2007
Applicant:
STMicroelectronics S.A.
Inventors:
Daniel Bensahel, Yves Campidelli, Olivier Kermarrec
Abstract: Method of compressing a digital image signal in which a first quantization step set, which is unique for a given segment, is determined so that the number of bits needed to encode the quantized data corresponding to this segment is greater than a target value. This first quantization step set then being modified, as a priority, for the blocks of the segment for which the gain, in the course of this modification, on the reduction of the number of bits needed to encode the quantized data corresponding to the segment to which it belongs, is the highest. This modification is carried out, on as many blocks as is necessary for the number of bits of this segment to be less than or equal to the target value. Device to implement this method.
Type:
Grant
Filed:
September 19, 2002
Date of Patent:
October 23, 2007
Assignees:
STMicroelectronics S.A., Group des Ecoles des Telecommunications, STMicroelectronics Asia Pacific Pte. Ltd.
Inventors:
Jean-Michel Bard, Jean-Luc Danger, Lucas Hui, Christophe Cunat
Abstract: A device for producing a video image sharpness improvement signal (DOC21-DOC22), with black level clipping of an associated video signal, comprises a differential transconductance stage processing the video signal and whose bias currents (Imax) are directly proportional to the active component (?V) of the video signal so as to bring about a black level sharpness improvement signal clipping.
Type:
Grant
Filed:
August 26, 2004
Date of Patent:
October 23, 2007
Assignee:
STMicroelectronics S.A.
Inventors:
Eric Cirot, Michel Barou, Danika Chaussy
Abstract: A structure formed in a semiconductor substrate having at least one area having a high concentration of atoms of a metal such as platinum or gold, in which the area is surrounded with at least one first trench penetrating into the substrate.
Abstract: A device for protecting an electronic circuit comprising a support to which are attached at least two circuit portions, each comprising at least one integrated circuit chip. The device comprises a wafer of a semiconductor material covered with a conductive layer arranged parallel to the support, the wafer being connected to the support by conductive pillars distributed around each circuit portion and in contact with the conductive layer.
Abstract: A method of COFDM demodulation of symbols, each including first carriers conveying data and pilots having their frequency positions varying at least partly from one symbol to the next symbol. The method includes, for each symbol, a step of determining a first estimate of the transfer function of the channel for each carrier in a set of the first carriers of the symbol such that, for the frequency positions of the considered carriers, symbols different from the symbol include pilots, corresponding to a linear combination of second estimates determined for pilots at the frequency of said carrier. The coefficients of the linear combination are determined in iterative fashion, a new coefficient value being equal to the sum of the last value of the coefficient and of a term including the product between an iteration step and an error term, the iteration step being determined in iterative fashion.
Abstract: A direct conversion type of frequency transposition device includes a transconductor block receiving the input signal and a current switching block connected to the output from the device. At least the common mode (Iif1+Iif2) is servocontrolled to static output currents from the frequency transposition device on a current proportional to a reference current (Iref) and independent of the static output currents from the transconductor block.
Type:
Grant
Filed:
August 27, 2003
Date of Patent:
October 9, 2007
Assignee:
STMicroelectronics S.A.
Inventors:
Bruno Pellat, Sylvie Gellida, Jean-Charles Grasset, Frédéric Rivoirard
Abstract: A method for transmitting data between two nodes of an orthogonal frequency-division multiplexing network, including assigning to each node at least one transmit frequency set and one receive frequency set, the transmit set of each node being different from its own receive set; and using each node as a relay for transmitting back a transmission which is not intended for it.
Abstract: A receiver for a digital data transmission device for receiving a digital signal and comprising a free sampler physically taking samples rk of a received signal r(t) at a frequency at least equal to twice the received signal spectrum maximum frequency. A digital interpolator allows to derive a sequence of samples Xk calculated from said physical samples, according to a tuning parameter ?. An equalizer adjustable to a set of equalization parameters e allows to process said interpolator output samples Xk. A computing unit simultaneously provides, in a single processing, values of ? to the digital interpolator and values of the equalization parameters e to the digital equalizer. The invention also provides a method for digitally processing a received signal in a digital transmission device.