Abstract: A method and a system for qualifying an integrated circuit according to a parasitic supply peak detector that it contains, including: supply of the integrated circuit to be tested under at least a first voltage; checking of a starting of the circuit; application of at least one first noise peak on the circuit power supply, while respecting an amplitude and time gauge; and comparison of average currents consumed by the circuit before and after the peak.

Abstract: A method and a circuit for marking with a binary code a video sequence compressed by motion calculation, from one picture to another, of macroblocks dividing each picture, the digital pictures being distributed in at least two categories according to whether they are coded integrally or by the motion vectors of the macroblocks with respect to the previous picture or to the previous and next pictures, which includes, at least for the pictures coded by motion vectors, only marking the macroblocks for which the motion vectors are greater than a predetermined threshold.

Abstract: An image sensor including a substrate of a semiconductor material having first and second opposite surfaces; at least one photodiode formed in the substrate on the first surface side and intended to be lit through the second surface; a stacking of insulating layers covering the first surface; and conductive regions formed at the stacking level. The sensor further includes a transparent insulating layer at least partly covering the second surface; a transparent conductive layer at least partly covering the transparent insulating layer; and circuitry for biasing the conductive layer.

Abstract: A phase locked loop includes a controlled oscillator for delivering an output signal at a determined output frequency, and a variable frequency divider for converting the output signal into a signal at divided frequency. The PLL is termed composite in that it includes at least one first loop having a loop filter for generating a first control signal for the oscillator on the basis of the signal at divided frequency, and a second loop having a loop filter, different from the loop filter of the first loop, for generating, on the basis of the signal at divided frequency, a second signal for additional control of the oscillator. The loop filter of the first loop and the loop filter of the second loop have different respective cutoff frequencies. The passband of the first loop, can be adapted to ensure the convergence and the stability of the PLL, while the second loop can afford extra passband increasing the speed of adaptation of the PLL in case of modification of the value of a preset for the output frequency.

Abstract: An arbitration method, for a data bus in an architecture having n functional blocks, regulates access to the bus. The method includes: receiving, at one of plural agents, information from one of the functional blocks via high level primitives. Each agent generates in response a critical rank vector comprising at least first and second components. An arbitrator receives the critical rank vectors generated by rival the agents and applies a maximum or minimum extracting mechanism to at least one of the two components of the critical rank vectors to uniquely identify the block accessing the resource. Thus, functional blocks can be separated from arbitration control, the agents implementing the arbitration control and being solely responsible for it.

Abstract: A method and a system for comparing a set of minutiae of a current image with a set of minutiae of a reference image, according to which the minutiae are sorted by their Cartesian coordinates in the image plane from a predetermined point of origin, a common path of similar minutiae is searched in the reference set and in the current set, and it is considered that there is an identity between the two images if the common path is comprised of a number of segments greater than a first threshold.

Abstract: A distributed phase shifter including: a first planar winding having its ends defining accesses in phase opposition; a second planar winding coupled with the first one and grounded by a first capacitive element; a third planar winding in a conductive level different from that receiving the first winding and electrically in series with the second winding; and a fourth planar winding, coupled with the third one in a conductive level different from that receiving the second winding, first ends of the third and fourth windings being connected by a capacitive element and their second ends being connected by another capacitive element, their first and second respective ends defining accesses in phase quadrature.

Abstract: An electrical connection device includes a platform and a moving head. Between these components a semiconductor component is received and retained. The semiconductor component includes an electrical connection plate bearing an integrated circuit chip. The platform supports the making of electrical connection with front electrical connection terminals provided on a front panel of the electrical connection plate. The moving head bears a printed circuit board having interlinked pairs of contact terminals and associated pairs of electrical connection posts which make contact between the pairs of contact terminals of the printed circuit board and rear link terminals and rear transfer terminals provided on a rear panel of the electrical connection plate. The electrical connection plate includes circuitry which electrically connects the rear link terminals to the chip and also circuitry which electrically connects rear transfer terminals to front transfer terminals.

Abstract: A distributed combiner/splitter having a first line formed of a first planar winding in a first conductive level and of a second planar winding in a second conductive level, and a second line formed of a third planar winding interdigited with the first winding in the first level, and of a fourth planar winding interdigited with the second winding in the second level, the windings having an increasing width from the outside to the inside.

Abstract: A method for cadence detection in a sequence of video fields is based on at least a search for cadence patterns in a sequence of bits representative of the motion in at least a part of the field from one field to another in the field sequence. The signaling of field skip and/or field repeat commands as applied to the fields in the field sequence is considered during the cadence detection operation so as to field skips and repeats.

Abstract: A semiconductor package and a process for fabricating such a package are presented. The package has a substantially parallelepipedal block, made of an encapsulation material. Embedded within the block is at least one integrated-circuit chip and a leadframe having functional leads for electrical connection to said chip. These functional leads emerge on the outside of said block via at least one side and are intended to be connected to a printed-circuit board. The leadframe does not have functional leads on at least one of the other sides of said block. For that other side, the leadframe includes auxiliary leads for electrical connection to said chip which emerge on the outside of said block via at least one of the sides of this block which do not have functional leads. These auxiliary lead are not intended to be connected to said printed-circuit board.

Abstract: An electronic system comprises an initiator module and a target module addressable by the initiator module, and an interface and control module for interfacing between respective communication protocols of the initiator module and of the target module. The interface and control module is constructed to set a composite instruction detection signal in response to the detection of a composite instruction executed by the initiator module, which composite instruction detection signal is used for the interfacing. The interface and control module is constructed to detect a composite instruction executed by the initiator module when, at a determined clock cycle of the initiator module, a change of the elementary operation executed by the initiator module is detected with respect to the previous clock cycle of the initiator module, while, at the same time, a signal for selecting the target module which was active is kept active.

Abstract: In a method for detecting the cadence of a sequence of images, each pixel in each current field in the sequence of images is compared to at least one pixel in at least one previous field. A pixel motion phase value is assigned to each pixel in the field as a function of the result of that comparison. For each block of pixels in the current field, a block motion phase value is determined from the motion phase values of the pixels in the block. The current field is segmented into at least one region, with each region comprising a whole number of blocks, as a function of at least the determined block motion phase values. A region motion phase value is assigned to each region, based on the block motion phase values for the blocks in the region.

Abstract: Data stored in a first memory are processed by a processing device comprising a processor, a second memory, and an interface device interfacing the processing device with the first memory. In the interface device, in order to facilitate transfer of data from the first memory where data are stored in a first data format to the second memory where data are stored in a second data format, a first group of data is received from the first memory, with said group ordered into a sequence corresponding to the first data format. Then at least one second group of data is obtained by ordering said data in the first group into a new sequence which is a function of the first and second data formats. The second group of data is stored in the second memory.

Abstract: An amplitude demodulation method and device comprising a converter sampling an input signal having its sampling frequency corresponding to three times the modulation carrier frequency.

Abstract: An interleaver includes two random access memories for storing data and an addressing device (100) linked to respective address inputs of the two memories. The addressing device is designed to transmit, at each instant of a clock, a cue for read access to one of the two memories and a cue for write access to the other of the two memories, so that, at each instant, a data item is written to or read from each memory.

Abstract: An electromagnetic transponder intended to draw the power necessary to its operation of from a field radiated by a terminal of transmission of a carrier at a first supply frequency and to back-modulate the received signal at the rate of a sub-carrier at a second frequency lower than the first one, and comprising means capable of demodulating and decoding signals modulated by said sub-carrier, as well as a system of communication between such transponders.

Abstract: An electronic circuit, having a test mode in application of the “internal scan path” technique, includes a plurality of configurable cells and a control circuit. The electronic circuit is adapted to working in a standard mode of operation or in a test mode during which the control circuit is active and configures the configurable cells either in a functional state or in a chained state. The electronic circuit furthermore includes a validation circuit that performs the following operations successively when it receives an instruction for changing the mode of operation (TEST, FIN) of the electronic circuit: produce initialization signals (INIT1, INIT2, . . . , INITN) to command the initialization of all the configurable cells, and then produce a mode-changing signal (VAL).

Abstract: A pump having: a cavity formed inside an insulating substrate, the upper part of the substrate being situated near the cavity having an edge; a conductive layer covering the inside of the cavity up to the edge and optionally covering the edge itself; a flexible membrane made of a conductive material placed above the cavity and resting against the edge; a dielectric layer covering the conductive layer or the membrane whereby insulating the portions of the conductive layer and of the membrane that are near one another; at least one aeration line formed in the insulating substrate that opens into the cavity via an opening in the conductive layer, and; terminals for applying a voltage between the conductive layer and the membrane.

Abstract: A method and a circuit for detecting an overheating of an electronic switch of power supply of a load by an A.C. voltage, in which a voltage representative of the temperature in the vicinity of the switch is compared with a threshold, the result of this comparison being sampled at frequency corresponding to an even multiple of the frequency of the A.C. power supply voltage, to provide a signal indicative of the fact that a temperature threshold has been exceeded.