Patents Assigned to STMicroelectronic S.r.l.
  • Publication number: 20230198386
    Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
    Type: Application
    Filed: February 14, 2023
    Publication date: June 22, 2023
    Applicants: STMicroelectronics International N.V., STMicroelectronics S.r.l.
    Inventors: Vikas Rana, Marco Pasotti, Fabio De Santis
  • Patent number: 11681141
    Abstract: A MEMS device is obtained by forming a temporary biasing structure on a semiconductor body, and forming an actuation coil on the semiconductor body, the actuation coil having at least one first end turn, one second end turn and an intermediate turn arranged between the first and the second end turns and electrically coupled to the first end turn through the temporary biasing structure. In this way, the intermediate turn is biased at approximately the same potential as the first end turn during galvanic growth, and, at the end of growth, the actuation coil has an approximately uniform thickness. At the end of galvanic growth, portions of the temporary biasing structure are selectively removed to electrically separate the first end turn from the intermediate turn and from a dummy biasing region adjacent to the first end turn.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: June 20, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Roberto Carminati, Sonia Costantini, Riccardo Gianola, Linda Montagna, Francesca Maria Carla Carpignano
  • Publication number: 20230187389
    Abstract: To manufacture a redistribution layer for an integrated circuit, a first insulating layer is formed on a conductive interconnection layer of a wafer. A conductive body is then formed in electrical contact with the interconnection layer. The conductive body is then covered with an insulating region having an aperture that exposes a surface of the conductive body. The surface of the conductive body and the insulating region are then covered with an insulating protection layer having a thickness less than 100 nm. This insulating protection layer is configured to provide a protection against oxidation and/or corrosion of the conductive body.
    Type: Application
    Filed: December 9, 2022
    Publication date: June 15, 2023
    Applicant: STMicroelectronics S.r.l.
    Inventors: Samuele SCIARRILLO, Paolo COLPANI
  • Publication number: 20230184806
    Abstract: An inertial structure is elastically coupled through a first elastic structure to a supporting structure so as to move along a sensing axis as a function of a quantity to be detected. The inertial structure includes first and second inertial masses which are elastically coupled together by a second elastic structure to enable movement of the second inertial mass along the sensing axis. The first elastic structure has a lower elastic constant than the second elastic structure so that, in presence of the quantity to be detected, the inertial structure moves in a sensing direction until the first inertial mass stops against a stop structure and the second elastic mass can move further in the sensing direction. Once the quantity to be detected ends, the second inertial mass moves in a direction opposite to the sensing direction and detaches the first inertial mass from the stop structure.
    Type: Application
    Filed: December 28, 2022
    Publication date: June 15, 2023
    Applicant: STMicroelectronics S.r.l.
    Inventors: Gabriele GATTERE, Francesco RIZZINI, Alessandro TOCCHIO
  • Patent number: 11675024
    Abstract: Hall sensing signals are received in a spinning readout pattern of subsequent readout phases, wherein the pattern is cyclically repeated at a spinning frequency and a polarity of the Hall sensor signals is reversed in two non-adjacent readout phases of the readout pattern. A signal storage circuit includes signal storage capacitors. An accumulation circuit includes accumulation capacitors. A switch network is selectively actuated to couple the signal storage capacitors with the accumulation capacitors synchronously with phases in the spinning readout pattern in subsequent alternating first and second periods. The spinning output is stored with alternating opposite signs on the signal storage capacitors and the Hall sensing signals are stored in the signal storage capacitors and then accumulated on the accumulation capacitors with alternate signs in subsequent periods. The accumulated output signal is then demodulated with a demodulation frequency half the spinning frequency.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: June 13, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Paolo Angelini, Roberto Pio Baorda, Danilo Karim Kaddouri
  • Patent number: 11675720
    Abstract: An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: June 13, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Lorenzo Re Fiorentin, Giampiero Borgonovo
  • Patent number: 11676434
    Abstract: A method includes performing, by a terminal with an access card, a first relay attack check for the access card in accordance with a local value associated with the terminal and a local value associated with the access card; determining, by the terminal, that the access card has passed the first relay attack check, and based thereon, performing, by the terminal with the access card, an authentication check of the access card in accordance with the local value associated with the terminal, the local value associated with the access card, and a local challenge value associated with the terminal; and determining, by the terminal, that the access card has passed the first relay attack check and the authentication check, and based thereon, validating, by the terminal, the access card.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: June 13, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Carlo Cimino, Luca Di Cosmo
  • Patent number: 11675186
    Abstract: A method for making a micro-electro mechanical (MEMS) device includes forming a MEMS mirror stack on a handle layer, and applying a first bonding layer to the MEMS mirror stack. The method continues with disposing a substrate on the first bonding layer such that the MEMS mirror stack is mechanically anchored to the substrate and so as to seal against ingress of environmental contaminants, removing the handle layer, and applying a second bonding layer to the MEMS mirror stack. A cap layer is disposed on the second bonding layer such that the cap layer is mechanically anchored to the MEMS mirror stack and so as to seal against ingress of environmental contaminants.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: June 13, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giorgio Allegato, Sonia Costantini, Federico Vercesi, Roberto Carminati
  • Patent number: 11673799
    Abstract: To manufacture an oscillating structure, a wafer is processed by: forming torsional elastic elements; forming a mobile element connected to the torsional elastic elements; processing the first side of the wafer to form a mechanical reinforcement structure; and processing the second side of said wafer by steps of chemical etching, deposition of metal material, and/or deposition of piezoelectric material. Processing of the first side of the wafer is carried out prior to processing of the second side of the wafer so as not to damage possible sensitive structures formed on the first side of the wafer.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: June 13, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Enri Duqi, Nicolo′ Boni, Lorenzo Baldo, Massimiliano Merli, Roberto Carminati
  • Patent number: 11677316
    Abstract: A variable duty cycle switching signal at a switching frequency is applied to a switching current regulation circuit arrangement energizing a current storage circuit assembly. Switching of the variable duty cycle switching signal is controlled by an upper and a lower threshold current level. The upper and lower threshold current levels vary with time following an average current value time variation. Additionally, frequency jitter is introduced in the variable duty cycle switching signal by: defining at least a frequency modulation window around a limit frequency identifying a limit value for an acceptable EMI; and applying an amplitude modulation of the upper and/or lower threshold current levels varying with time, wherein the amplitude modulation is applied in a time interval between times when the switching frequency enters and exit the frequency window.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: June 13, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Sebastiano Messina, Marco Torrisi
  • Patent number: 11669168
    Abstract: A system for detection of a touch gesture of a user on a detection surface includes a processing unit, an electrostatic-charge-variation sensor, which generates a charge-variation signal; and an accelerometer, which generates an acceleration signal. The processing unit is configured to: detect, in the charge-variation signal, a first feature identifying the touch; detect, in the acceleration signal, a second feature identifying the touch; detect a temporal correspondence between the first and second features identifying the touch gesture; and validate the touch gesture only in the case where both the first and second features have been detected and the temporal correspondence satisfies a pre-set relation.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: June 6, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Fabio Passaniti, Enrico Rosario Alessi
  • Patent number: 11671009
    Abstract: An embodiment DC switching converter comprises first and second Zeta converters, each comprising an input stage, an output stage, a first switching stage, and a second switching stage. The input stage of each Zeta converter comprises a respective input inductor having a first terminal electrically coupled to the respective first switching stage. The input inductors of the input stages of the first and second Zeta converters are magnetically coupled in such a way that when current enters the terminal of the input inductor of the first Zeta converter that is coupled to the first switch stage of the first Zeta converter, a voltage induced by the coupled current is positive at the terminal of the input inductor of the second Zeta converter that is coupled to the first switching stage of the second Zeta converter.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: June 6, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventor: Edoardo Botti
  • Publication number: 20230170022
    Abstract: A phase change memory element has a memory region, a first electrode and a second electrode. The memory region is arranged between the first and the second electrodes and has a bulk zone and an active zone. The memory region is made of a germanium, antimony and tellurium based alloy, wherein germanium is in a higher percentage than antimony and tellurium in the bulk zone of the memory region. The active zone is configured to switch between a first stable state associated with a first memory logic level and a second stable state associated with a second memory logic level. The active zone has, in the first stable state, a uniform, amorphous structure and, in the second stable state, a differential polycrystalline structure including a first portion, having a first stoichiometry, and a second portion, having a second stoichiometry different from the first stoichiometry.
    Type: Application
    Filed: November 23, 2022
    Publication date: June 1, 2023
    Applicant: STMicroelectronics S.r.l.
    Inventors: Elisa PETRONI, Andrea REDAELLI
  • Publication number: 20230170283
    Abstract: A “double-deck” semiconductor device includes a first semiconductor chip mounted to a first surface of a leadframe, with a first wire bonding pattern and a first mass of encapsulating material molded onto the first surface of the leadframe when the leadframe is in a first spatial orientation. The leadframe with the first semiconductor chip and the first wire bonding pattern encapsulated and thus protected by the first mass of encapsulating material is then turned over to a second spatial orientation. A second semiconductor chip is attached to the second surface of the leadframe, with a second wire bonding pattern and a second mass of encapsulating material, different from the first mass of encapsulating material molded onto the second surface of the leadframe.
    Type: Application
    Filed: November 29, 2022
    Publication date: June 1, 2023
    Applicant: STMicroelectronics S.r.l.
    Inventor: Paolo CREMA
  • Patent number: 11664849
    Abstract: A communication network comprises a plurality of electronic devices coupled via a plurality of communication links. The communication links comprise links over a first physical medium and links over a second physical medium. A method of operating the network comprises issuing, at an originator device, a path request message directed towards a destination device, transmitting the path request message from the originator device to the destination device through a first set of intermediate devices via a forward sequence of links, issuing, at the destination device, a path reply message directed towards the originator device, and transmitting the path reply message from the destination device to the originator device through a second set of intermediate devices via a reverse sequence of links.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: May 30, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Matteo Varesio, Paolo Treffiletti
  • Patent number: 11665915
    Abstract: According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: May 30, 2023
    Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.
    Inventors: Fabio De Santis, Vikas Rana
  • Patent number: 11658674
    Abstract: In an embodiment, a circuit includes N sensing channels. Each channel includes a first main sensing node and a second redundancy sensing node paired therewith. N analog-to-digital converters (ADCs) are coupled to the first sensing nodes, with digital processing circuits coupled to the N ADCs. A pair of multiplexers are coupled to the second sensing nodes and to the N ADCs with a further ADC coupled to the output of the second multiplexer. An error checking circuit is coupled to the outputs of the second multiplexer and the further ADC to compare, at each time window in a sequence of N time windows, a first digital value and a second digital value resulting from conversion to digital of: an analog sensing signal at one of the first sensing nodes, and an analog sensing signal at the second sensing node paired with the selected one of the first sensing nodes.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: May 23, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Nicola Errico, Marzia Annovazzi, Alessandro Cannone, Enrico Ferrara, Gea Donzelli, Paolo Turbanti
  • Patent number: 11656539
    Abstract: A microelectromechanical device includes a fixed structure defining a cavity with a tiltable structure that is elastically suspended in the cavity. A piezoelectrically driven actuation structure, interposed between the tiltable structure and the fixed structure, is biased for causing rotation of the tiltable structure about a first rotation axis belonging to a horizontal plane in which the tiltable structure rests. The actuation structure includes a pair of driving arms carry respective regions of piezoelectric material and are elastically coupled to the tiltable structure on opposite sides of the first rotation axis through respective elastic decoupling elements. The elastic decoupling elements exhibit stiffness in regard to movements out of the horizontal plane and compliance to torsion about the first rotation axis.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: May 23, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Nicolo′ Boni, Roberto Carminati, Massimiliano Merli
  • Patent number: 11658646
    Abstract: In an embodiment, a circuit for tripling frequency is configured to receive an input voltage (Vin) having a sinusoidal shape and a base frequency. The circuit has a first and a second transistor pair that are cross-coupled, and a trans-characteristics f(Vin) approximating a polynomial nominal trans-characteristic given by f ? ( V i ? n ) = ( 3 A ? V i ? n - 4 A 3 ? V i ? n 3 ) ? g m where A represents an amplitude of the input voltage and gm is a transconductance of transistors of the first and second transistor pairs.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: May 23, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mahmoud Mahdipour Pirbazari, Andrea Mazzanti, Andrea Pallotta
  • Patent number: 11655140
    Abstract: A micro-electro-mechanical device is formed by a fixed structure having a cavity. A tiltable structure is elastically suspended over the cavity and has a main extension in a tiltable plane and is rotatable about a rotation axis parallel to the tiltable plane. A piezoelectric actuation structure includes first and second driving arms carrying respective piezoelectric material regions and extending on opposite sides of the rotation axis. The first and the second driving arms are rigidly coupled to the fixed structure and are elastically coupled to the tiltable structure. During operation, a stop structure limits movements of the tiltable structure with respect to the actuation structure along a planar direction perpendicular to the rotation axis. The stop structure has a first planar stop element formed between the first driving arm and the tiltable structure and a second planar stop element formed between the second driving arm and the tiltable structure.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: May 23, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Nicolo' Boni, Roberto Carminati, Massimiliano Merli