Abstract: A field effect transistor has a semiconductor layer with a top surface extending in a horizontal plane, and an active area defined in which are trench gate regions, which extend in depth with respect to the top surface and have an insulating coating layer and a conductive inner layer, and source regions, adjacent to the trench gate regions so as to form a conductive channel extending vertically. The trench gate regions have a plurality of first gate regions, which extend in length in the form of stripes through the active area along a first direction of the horizontal plane, and moreover a plurality of second gate regions, which extend in length in the form of stripes through the same active area along a second direction of the horizontal plane, orthogonal to, and crossing, the first gate regions. In particular, the first gate regions and second gate regions cross in the active area, joining with a non-zero curvature radius.

Abstract: A first switch couples an input node receiving a main control signal for a main switching stage of a multi-phase converter to an output node delivering a secondary control signal for a secondary switching stage following actuation of the secondary switching stage. A second switch couples the output node to a capacitor during a time period of actuation/deactuation of the secondary switching stage. Current is sourced to the capacitor during the actuation time period or sunk from the capacitor during the deactuation time period. The sourced or sunk current may be generated proportional to the main control signal.

Abstract: An optical sensor includes at least one photodetector configured to be reverse biased at a voltage exceeding a breakdown voltage by an excess bias voltage. At least one control unit is configured to adjust the reverse bias of the at least one photodetector. A method of operating an optical sensor is also disclosed.

Abstract: A protection device includes a first inductive element connecting first and second terminals and a second inductive element connecting third and fourth terminals. A first component includes a first avalanche diode connected in parallel with a first diode string, anodes of the first avalanche diode and a last diode in the string being connected to ground, cathodes of the first avalanche diode and a first diode in the string being connected, and a tap of the first diode string being connected to the first terminal. A second protection component includes a second avalanche diode connected in parallel with a second diode string, anodes of the second avalanche diode and a last diode in the string being connected to ground, cathodes of the second avalanche diode and a first diode in the string being connected, and a tap of the second diode string being connected to the third terminal.

Abstract: A semiconductor chip includes an electrical contact layer covered by a passivation layer. The semiconductor chip is encapsulated in an encapsulation formed by laser-direct-structuring (LDS) material. Laser beam energy is applied to the encapsulation to structure therein a through via passing through the encapsulation and removing the passivation layer at a bonding site of the electrical contact layer of the at least one semiconductor chip. The through via structured in the encapsulation is made electrically conductive so that the electrically-conductive through via is electrically coupled to, optionally in direct contact with, the electrical contact layer at a bonding site where the passivation layer has been removed.

Abstract: An antenna-in-package semiconductor device includes a semiconductor chip coupled to a planar substrate. An encapsulation body encapsulates the semiconductor chip. The encapsulation body includes a through cavity extending to the planar substrate. A rectilinear wire antenna is mounted within the through cavity and extends, for instance from the planar substrate, along an axis that is transverse to a surface of the planar substrate to which the semiconductor chip is coupled. The rectilinear wire antenna is electrically coupled to the semiconductor chip. An insulating material fills the cavity to encapsulated the rectilinear wire antenna.

Abstract: The disclosure concerns an electronic device and methods of making an electronic device. The electronic device includes a circuit that is at least partially formed in an active region of a substrate. An electronic package is stacked on the substrate. A via extends through the circuit from the active region of the substrate to a surface of the substrate that is opposite the active region. At least one contacting element connects the via to the electronic package.

Abstract: An electronic cell includes an integrated stack of structures including, successively: a first electrode; an ovonic threshold switch layer below the first electrode; and a fixed resistor below the ovonic threshold switch layer. A second electrode may be included between fixed resistor and the ovonic threshold switch layer. A memory layer, for example a phase change material layer, a resistive random-access memory layer or a magneto-resistive random-access memory layer, may be included between the first electrode and the ovonic threshold switch layer.

Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.

Abstract: A method is provided that is implemented by a first NFC device configured in reader mode. The method includes evaluating an information about the coupling between the first NFC device and a second NFC device configured in card mode, as a function of the position of an antenna of the first NFC device with respect to an antenna of the second NFC device. The method further includes indicating the information by a user interface of the first device.

Abstract: A method selects one or a plurality of sets of values characterizing an electric power of a power source capable of powering a device coupled to the power source via a connection interface. The selection is carried out according to values, characterizing the power supplied by the power source, measured at the connection interface.

Abstract: An embedded system includes a peripheral and system-on-a-chip executing virtual machines and a hypervisor. The peripheral includes a crossbar circuit receiving digital sensor signals and selectively outputting the digital sensor signals to different outputs, queue circuits each receiving a different one of the digital sensor signals from the crossbar circuit, and queue protection circuits associated with the queue circuits and selectively permitting access to one of the queue circuits by the virtual machines. The hypervisor controls the queue protection circuits to set which of the virtual machines may access which queue circuits. A sensor protection circuit selectively permits reading of the digital sensor signals from the crossbar circuit by the queue circuits. The hypervisor controls the sensor protection circuit to set which of the queue circuits may access each of the digital sensor signals from the crossbar circuit.

Abstract: Image sensors and methods of manufacturing image sensors are provided. One such method includes forming a structure that includes a semiconductor layer extending from a front side to a back side, and a capacitive insulation wall extending through the semiconductor layer. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductor or a semiconductor material. Portions of the semiconductor layer and the region of the conductor or semiconductor material are selectively etched, and the first and second insulating walls have portions protruding outwardly beyond a back side of the semiconductor layer and of the region of the conductor or semiconductor material. A dielectric passivation layer is deposited on the back side of the structure, and portions of the dielectric passivation layer are locally removed on a back side of the protruding portions of the first and second insulating walls.

Abstract: Thyristor semiconductor device comprising an anode region, a first base region and a second base region having opposite types of conductivity, and a cathode region, all superimposed along a vertical axis.

Abstract: A memory calibration system includes a memory array having a plurality of memory cells, a sensing circuit coupled to the memory array, and calibration circuitry. A pattern of test data is applied to the memory array in order to generate calibration information based on output provided by the first sensing circuit in response to the application of the pattern of test data to the memory array. The generated calibration information is stored in a distributed manner within memory cells of the memory array. Some of the generated calibration information may be combined with data values stored in the plurality of memory cells as part of one or more operations on the stored data values.

Abstract: In accordance with embodiments, methods for the recovery of security credentials of a Bluetooth mesh network are disclosed. A computing device of the Bluetooth mesh network receives user login information, and generates a network key of the Bluetooth mesh network based on the user login information. The computing device generates an application key of a first node to be provisioned based on user login information. A device key is generated using the unicast address of the first node and part of user credentials. The current sequence number is recovered by one of the four techniques depending on the characteristics of the network. The unicast addresses of the nodes are assumed to be sequential and later validated by sending messages. IV index is recovered using processes defined in the Bluetooth mesh standard. After recovery of the above parameters, the mesh network can operate normally using the aforementioned computing device.

Abstract: A register bank of a channel of a direct memory access circuit is initialized. Transfer cycles are executed as configured by the register bank, and updates are made to the registers from a memory. At each transfer cycle, an operation is performed in accordance with a first field of the register bank to either: carry on the execution or generate a first signal and suspend the execution. In response to each reception of the first signal by a central processing unit, an operation is performed to either: generate a second signal or modify the content of the register band and/or record into the memory a first item representative of a next update of the register bank. A second signal is then generated.

Abstract: A contactless device includes an impedance matching and filter circuit connected to an antenna and being on the one hand operable for contactlessly communicating with a second device via the antenna, and on the other hand operable for contactlessly charging a rechargeable power supply of a third device via the antenna. A method of control includes modifying the impedance matching and filter circuit of the contactless device depending on whether the contactless device carries out the contactless communication or carries out the contactless charging.

Abstract: Disclosed herein is a method of making a microelectromechanical (MEMS) device. The method includes, in a single structural layer, affixing a tiltable structure to an anchorage portion with first and second supporting arms extending between the anchorage portion and opposite sides of the tiltable structure, and forming first and second resonant piezoelectric actuation structures extending between a constraint portion of the first supporting arm and the anchorage portion, on opposite sides of the first supporting arm. The method further includes coupling a handling wafer underneath the structural layer to define a cavity therebetween, and forming a passivation layer over the structural layer, the passivation layer having contact openings defined therein for routing metal regions for electrical coupling to respective electrical contact pads, the electrical contact pads being electrically connected to the first and second resonant piezoelectric actuation structures.

Abstract: A germanium waveguide is formed from a P-type silicon substrate that is coated with a heavily-doped N-type germanium layer and a first N-type doped silicon layer. Trenches are etched into the silicon substrate to form a stack of a substrate strip, a germanium strip, and a first silicon strip. This structure is then coated with a silicon nitride layer.