Abstract: An electronic integrated circuit chip includes a semiconductor substrate with a front side and a back side. A first reflective shield is positioned adjacent the front side of the semiconductor substrate and a second reflective shield is positioned adjacent the back side of the semiconductor substrate. Photons are emitted by a photon source to pass through the semiconductor substrate and bounce off the first and second reflective shields to reach a photon detector at the front side of the semiconductor substrate. The detected photons are processed in order to determine whether to issue an alert indicating the existence of an attack on the electronic integrated circuit chip.

Abstract: First and second n-channel FETs are connected in series between first and second terminals with an intermediate switching node. First and second driver circuits drive gates of the first and second n-channel FETs, respectively, in response to drive signals. The first driver circuit does not implement slew-rate control. A first resistor and capacitor are connected in series between the output of the first driver circuit and an intermediate node. A first electronic switch is connected between the intermediate node and the first terminal. A second electronic switch is connected between the intermediate node and the gate terminal of the first n-channel FET. A second resistor and a third electronic switch are connected in series between the gate terminal of the first n-channel FET and the switching node. A control circuit generates the drive signals and a first, second and third control signal for the first, second and third electronic switch.

Abstract: A semiconductor layer is doped with a first doping type and has an upper surface. A first electrode insulated from the semiconductor layer extending through the semiconductor layer from the upper surface. A second electrode insulated from the semiconductor layer extends through the semiconductor layer from the upper surface. The first and second electrodes are biased by a voltage to produce an electrostatic field within the semiconductor layer causing the formation of a depletion region. The depletion region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at first and second oppositely doped regions within the semiconductor substrate.

Abstract: A BiMOS-type transistor includes a gate region, a channel under the gate region, a first channel contact region and a second channel contact region. The first channel contact region is electrically coupled to the gate region to receive a first potential. The second channel contact region is electrically coupled to receive a second potential.

Abstract: A system comprising includes a wireless power receiver generating a rectified voltage. A low dropout regulator (LDO) generates a first regulated output voltage from the rectified voltage, during a first phase. A first switch couples the first regulated output voltage to a voltage output node during the first phase. During a second phase, the LDO generates a second regulated output voltage from the rectified voltage. A switching regulator generates a third regulated output voltage during the second phase. A second switch couples the third regulated output voltage to the voltage output node during the second phase. During a third phase, the LDO is disabled, while the switching regulator continues to generate the third regulated output voltage. The first switch opens during the third phase while the second switch remains closed.

Abstract: A three-phase load is powered by a PWM (e.g., SVPWM) driven DC-AC inverter having a single shunt-topology. A shunt voltage and a branch voltage of the inverter (across a transistor to be calibrated) are measured during a second period of each SVPWM sector, and the drain-to-source resistance of the calibrated transistor is calculated. During the fourth period of each SVPWM sector, the branch voltage is measured again, and another branch voltage across another transistor is measured. Using the drain-to-source resistance of the calibrated transistor and the voltage across the calibrated transistor measured during the fourth period, the phase current through the calibrated transistor is calculated. Using the other branch voltage measured during the fourth period and the drain-to-source resistance of its corresponding transistor (known from a prior SVPWM sector), the phase current through that transistor is calculated. From the two calculated phase currents, the other phase current can be calculated.

Abstract: An electronic module for generating light pulses includes an electronic card or interposer, a LASER-diode lighting module, and a LASER-diode driver module. The interposer has an edge recess in which the lighting module is completely inserted. The driver module is arranged on top of the interposer and the lighting module. The electrical connections for driving the LASER diodes are obtained without resorting to wire bonding in order to reduce the parasitic inductances.

Abstract: A time based boost DC-DC converter generates an output voltage using an inductor. A voltage error between the output voltage and a reference voltage is determined and processed in a) an integral control branch which converts the voltage error into an integral control current signal used to control a current controlled oscillator, and b) a proportional branch which converts the voltage error into a proportional control current signal used to control signal a delay line. Current flowing in the inductor is sensed, attenuated and used to apply adjustment to the integral and proportional control current signals. The output from the current controlled oscillator is passed through the delay line and phase detected in order to generate pulse width modulation (PWM) control signaling driving switch operation in the converter.

Abstract: An opaque dielectric carrier and confinement substrate is formed by a stack of layers laminated on each other. The stack includes a solid back layer and a front frame having a peripheral wall and an intermediate partition which delimits two cavities located on top of the solid back layer and on either side of the intermediate partition. Electronic integrated circuit (IC) chips are located inside the cavities and mounted on top of the solid back layer. Each IC chip includes an integrated optical element. Electrical connections are provided between the IC chips and back electrical contacts of the solid back layer. Transparent encapsulation blocks are molded in the cavities to embed the IC chips.

Abstract: A vertical capacitor includes a stack of layers conformally covering walls of a first material. The walls extend from a substrate made of a second material different from the first material.

Abstract: A protection circuit for a transistor switch coupled to a power supply rail operates to modulate a control voltage at a control terminal of the transistor switch. A first circuit detects an overload across the terminals of the switch with respect to a threshold to generate a signal which modulates the control voltage. A second circuit operates to adjust a value of the threshold in response to sensed variations in a supply voltage at the power supply rail.

Abstract: A contactless transponder includes a non-volatile static random access memory including memory points. Each memory point is formed by a volatile memory cell and a non-volatile memory cell. A protocol processing circuit receives data and stores the received data in the volatile memory cells of the memory. A write processing circuit is configured, at the end of the reception and storage of the data, to record, in a single write cycle, the data from the volatile memory cells to the non-volatile memory cells of the respective memory points.

Abstract: An apparatus includes a load pair including a first transistor and a second transistor, a common mode feedback circuit comprising a first common mode feedback transistor and a second common mode feedback transistor, wherein a drain of the first common mode feedback transistor is coupled to a source of the first transistor, and a gate of the first common mode feedback transistor is coupled to a drain of the first transistor, and a drain of the second common mode feedback transistor is coupled to a source of the second transistor, and a gate of the second common mode feedback transistor is coupled to a drain of the second transistor, and an offset cancellation stage coupled to outputs of the load pair.

Abstract: A method of reducing power consumption in portable devices includes providing a sensor producing a sensing signal indicative of sensed entity and powering the sensor. Powering the sensor includes providing a first power value for a first time interval, providing a second power value for a second time interval, the second power value being different from the first power value, and discontinuing powering for a third time interval.

Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.

Abstract: A method includes receiving, by a device, of a control signal identifying a first application from among a plurality of compressed applications stored in a non-volatile memory of the device. The first application is stored in a first location of the non-volatile memory. The device decompresses the first application. The decompressing includes storing the decompressed first application into the non-volatile memory at least partially into the first location, and into a second location storing a second compressed application among the plurality of applications. The decompressed first application overwriting at least a portion of the second compressed application. The method may be performed as part of a customization process of an integrated circuit including the non-volatile memory.

Abstract: An electronic device includes a magnetometer that outputs magnetometer sensor signals and a gyroscope that outputs gyroscope sensor signals. The electronic device includes a magnetometer calibration module that calibrates the magnetometer utilizing the gyroscope sensor signals. The electronic device generates a first magnetometer calibration parameter based on a Kalman filter process. The electronic device generates a second magnetometer calibration parameter based on a least squares estimation process.

Abstract: A PLL includes an input comparison circuit comparing a reference signal to a divided feedback signal to thereby control a charge pump that generates a charge pump output signal. A filter receives the charge pump output signal when a switch is closed, and produces an oscillator control signal causing an oscillator to generate an output signal. Divider circuitry divides the output signal by a divisor to produce the divided feedback signal. Divisor generation circuitry changes the divisor over time so the output signal ramps from a start frequency to an end frequency. Modification circuitry stores a first oscillator control signal equal to the value of the oscillator control signal when the frequency of the output signal is the start ramp frequency. When the frequency of the output signal reaches the end ramp frequency, the switch is opened, and the stored first oscillator control signal is applied to the loop filter.

Abstract: A device includes a diode. The anode of the diode includes first, second, and third areas. The first area partially covers the second area and has a first doping level greater than a second doping level of the second area. The second area partially covers the third area and has the second doping level greater than a third doping level of the third area. A first insulating layer partially overlaps the first and second areas.

Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem include a clock edge selector configured to determine a phase difference between the first clock signal and the second clock signal and to select, based on the phase difference, either a rising edge or a falling edge of the second clock signal to control output of data from the first subsystem to the second subsystem.