Patents Assigned to STMicroelectronics (Crolles 2)
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Publication number: 20200035623Abstract: An integrated circuit is protected against at attack. An electrically conductive body at floating potential is situated in the integrated circuit. The electrically conductive body has an initial amount of electric charge prior to the attack and functions to collect electric charge as a result of the attack. A detection circuit operates to detect an amount of electric charge collected on the electrically conductive body and determine whether the collected amount is different from the initial amount. If the detected amount of charge is different from the initial amount, a control circuit trigger the taking of a protective action.Type: ApplicationFiled: July 22, 2019Publication date: January 30, 2020Applicant: STMicroelectronics (Rousset) SASInventors: Pascal FORNARA, Fabrice MARINET
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Patent number: 10545193Abstract: One or more embodiments are directed to charge pump overload detection circuits which may be employed in imaging devices including one or more SPAD arrays, such as proximity sensors and time of flight sensors. One embodiment is directed to a charge pump overload detection circuit that includes a charge pump, a charge pump supply regulation device, a charge pump voltage regulation feedback loop and a charge pump overload detection comparator. The charge pump supplies an output voltage to a load, and the charge pump supply regulation device supplies a regulated voltage to an input of the charge pump. The charge pump voltage regulation feedback loop includes a feedback voltage generator that generates a feedback voltage based on the charge pump output voltage, and an amplifier that generates and provides a charge pump regulation control signal to the charge pump supply regulation device based on a difference between the feedback voltage and a reference voltage.Type: GrantFiled: July 13, 2016Date of Patent: January 28, 2020Assignee: STMicroelectronics (Research & Development) LimitedInventor: John Kevin Moore
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Patent number: 10543504Abstract: A microfluidic die is disclosed that includes a plurality of heaters above a substrate, a plurality of chambers and nozzles above the heaters, a plurality of first contacts coupled to the heaters, and a plurality of second contacts coupled to the heaters. The plurality of second contacts are coupled to each other and coupled to ground. The die includes a plurality of contact pads, a first signal line coupled to the plurality of second contacts and to a first one of the plurality of contact pads, and a plurality of second signal lines, each second signal line being coupled to one of the plurality of first contacts, groups of the second signal lines being coupled together to drive a group of the plurality of heaters with a single signal, each group of the second signal lines being coupled to a remaining one of the plurality of contact pads.Type: GrantFiled: June 28, 2017Date of Patent: January 28, 2020Assignees: STMicroelectronics, Inc., STMICROELECTRONICS S.R.L., STMicroelectronics International N.V.Inventors: Simon Dodd, Joe Scheffelin, Dave Hunt, Matt Giere, Dana Gruenbacher, Faiz Sherman
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Patent number: 10547171Abstract: A power transistor supplying power to a load is coupled to a current limiter circuit including a differential amplifier that operates to detect a difference between a sense voltage, indicative of a load current, and a voltage reference. A control terminal of the power transistor is driven by a first output of the differential amplifier as a function of the detected difference. A voltage clamp circuit coupled to an input terminal generates a floating ground. A short-circuit protection circuit coupled to the floating ground and interposed between a second output of the differential amplifier and the control terminal of the power transistor provides a short-circuit protection for the first output of the differential amplifier. A reaction time circuit is coupled between the first and second outputs of the differential amplifier and a source terminal of the power transistor to limit a short-circuit current at the source terminal.Type: GrantFiled: May 16, 2017Date of Patent: January 28, 2020Assignee: STMicroelectronics S.r.l.Inventors: Ignazio Bruno Mirabella, Francesco Pulvirenti, Salvatore Pappalardo
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Publication number: 20200029058Abstract: A light projection system includes a GPU that receives video data containing video images, defines a two-dimensional grid (each element of which represents a position of a light beam at a different time), designates which elements of the two-dimensional grid correspond to positions of the light beam in a designated area, designates which elements correspond to positions of the light beam outside of the designated area with some positions outside being designated as calibration positions, maps each element corresponding to positions in the designated area to a corresponding pixel of a frame of a video image, and maps elements corresponding to calibration positions to calibration pixels. An ASIC receives the mapped pixels and mapped calibration pixels from the GPU, and generates a beam position control signal therefrom. A controller controls a movable mirror based on the beam position control signal.Type: ApplicationFiled: September 27, 2019Publication date: January 23, 2020Applicants: STMicroelectronics S.r.l., STMicroelectronics LtdInventors: Massimo RATTI, Eli YASER, Naomi PETRUSHEVSKY, Yotam NACHMIAS
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Patent number: 10541079Abstract: An integrated transformer includes a primary winding and a secondary winding each having a spiral planar arrangement coils. A dielectric portion of dielectric material is interposed between the primary winding and the secondary winding. A field plate winding is electrically coupled with the primary winding. The field plate winding includes at least one field plate coil having a first lateral extension greater than a second lateral extension of a primary outer coil of the primary winding. The field plate coil is superimposed in plan view to the primary outer coil of the primary winding.Type: GrantFiled: February 5, 2019Date of Patent: January 21, 2020Assignee: STMicroelectronics S.r.l.Inventors: Vincenzo Palumbo, Gabriella Ghidini, Enzo Carollo, Fabrizio Fausto Renzo Toia
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Patent number: 10541692Abstract: A delay locked loop includes a control loop receiving reference and feedback clock signals, and generating biasing voltages therefrom. A delay chain receives the reference clock signal and generates N successively delayed versions thereof, each at a successive tap thereof. The Nth delayed version is the feedback clock signal. The control loop has a phase detector asserting an up signal when a phase of the feedback clock signal lags that of the reference clock signal, asserting a down signal when the phase of the feedback clock signal leads that of the reference clock signal. A digital filtering block compares a number of assertions of the up signal during the period of the reference clock signal to those of the down signal, and asserts an up or down command signal based thereupon. A biasing voltage generation circuit receives the up and down command signals and generates the biasing voltages therefrom.Type: GrantFiled: June 27, 2019Date of Patent: January 21, 2020Assignees: STMicroelectronics S.r.l., Politecnico Di MilanoInventors: Marco Zamprogno, Alireza Tajfar
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Patent number: 10541089Abstract: A capacitor has a variable capacitance settable by a bias voltage. A method for setting the bias voltage including the steps of: (a) injecting a constant current to bias the capacitor; (b) measuring the capacitor voltage at the end of a time interval; (c) calculating the capacitance value obtained at the end of the time interval; (d) comparing this value with a desired value; and (e) repeating steps (a) to (d) so as long as the calculated value is different from the set point value. When calculated value matches the set point value; the measured capacitor voltage is stored as a bias voltage to be applied to the capacitor for setting the variable capacitance.Type: GrantFiled: January 5, 2018Date of Patent: January 21, 2020Assignee: STMicroelectronics (Tours) SASInventor: Sylvain Charley
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Patent number: 10541196Abstract: The present disclosure is directed to a leadframe package having solder wettable sidewalls that is formed using a pre-molded leadframe and methods of manufacturing the same. A metal plated leadframe with a plurality of recesses and a plurality of apertures is placed into a top and bottom mold tool. A molding compound is then formed in the plurality of recesses and apertures in the leadframe to form a pre-molded leadframe. A plurality of die and wires are coupled to the pre-molded leadframe and the resulting combination is covered in an encapsulant. Alternatively, a bare leadframe can be processed and the metal layer can be applied after encapsulation. A saw or other cutting means is used for singulation to form leadframe packages. Each resulting leadframe package has a solder wettable sidewall for improving the strength of solder joints between the package and a circuit board.Type: GrantFiled: August 21, 2018Date of Patent: January 21, 2020Assignee: STMicroelectronics, Inc.Inventors: Aaron Cadag, Ernesto Antilano, Jr., Ela Mia Cadag
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Patent number: 10540663Abstract: The authenticity of a product associated with a host device is verified through a process. The product contains, in segments of a non-volatile memory, several different functions stored in ciphered fashion. The process involves, in a first phase, the sending by the host device of a control signal for executing a function, with the product functioning to decipher the function and store the unciphered function in the non-volatile memory. The process further involves, in a second phase, the sending by the host device of a control signal for causing execution of the deciphered function, with the product functioning to execute the function and send a result of this execution back to the host device. The host device evaluates the received result to verify product authenticity.Type: GrantFiled: February 20, 2018Date of Patent: January 21, 2020Assignee: STMicroelectronics (Rousset) SASInventors: Denis Farison, Fabrice Romain, Christophe Laurencin
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Patent number: 10541088Abstract: A capacitor has a variable capacitance settable by a bias voltage. A method for setting the bias voltage including the steps of: (a) injecting a constant current to bias the capacitor; (b) measuring the capacitor voltage at the end of a time interval; (c) calculating the capacitance value obtained at the end of the time interval; (d) comparing this value with a desired value; and (e) repeating steps (a) to (d) so as long as the calculated value is different from the set point value. When calculated value matches the set point value; the measured capacitor voltage is stored as a bias voltage to be applied to the capacitor for setting the variable capacitance.Type: GrantFiled: January 5, 2018Date of Patent: January 21, 2020Assignee: STMicroelectronics (Tours) SASInventor: Sylvain Charley
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Patent number: 10541677Abstract: A voltage generator circuit uses a feedback loop to regulate an output voltage at an output node. A pair of opposite conductivity source-follower transistors are coupled to the output node. A first one of the source-follower transistors operates to provide a fast current transient for charging a capacitive load that is switchably connected to the output node. A second one of the source-follower transistor operate under feedback control to regulate the voltage level at the output node.Type: GrantFiled: October 10, 2018Date of Patent: January 21, 2020Assignee: STMicroelectronics, Inc.Inventor: Pavan Nallamothu
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METHOD FOR MANUFACTURING A COVER FOR AN ELECTRONIC PACKAGE AND ELECTRONIC PACKAGE COMPRISING A COVER
Publication number: 20200020815Abstract: A cover for an electronic package is manufactured by placing an optical insert, having opposite faces and configured to allow light radiation to pass therethrough, between two opposite faces of a cavity of a mold in a position such that said optical faces of the optical insert make contact with said opposite faces of the cavity of the mold. A coating material is injected into the cavity and around the optical insert. The coating material is set to obtain a substrate that is overmolded around the optical insert so as to produce the cover. An electronic package includes an electronic chip mounted to a support substrate with the cover formed by the overmolded substrate mounted to the support substrate.Type: ApplicationFiled: September 25, 2019Publication date: January 16, 2020Applicant: STMicroelectronics (Grenoble 2) SASInventors: Karine SAXOD, Alexandre MAS, Eric SAUGIER, Gaetan LOBASCIO, Benoit BESANCON -
Publication number: 20200019269Abstract: Disclosed herein is a touch screen controller including input circuitry operating a touch screen, and processing circuitry cooperating with the input circuitry to acquire mutual touch data and self touch data from the touch screen, sum values of the mutual touch data to produce mutual sums, normalize the mutual sums and the self touch data, and calculate differences between the normalized self touch data and the normalized mutual sums. The touch screen controller enters into a floating mode if a largest difference that is positive is greater than a positive difference threshold and if a smallest difference value that is negative is less than a negative difference threshold, but enters a non-floating mode if the largest difference that is positive is less than the positive difference threshold or if the smallest difference value that is negative is less than the negative difference threshold.Type: ApplicationFiled: July 12, 2018Publication date: January 16, 2020Applicant: STMicroelectronics Asia Pacific Pte LtdInventors: Aiden JEON, Kai LIM
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Publication number: 20200020589Abstract: A strip made of a semiconductor material is formed over a substrate. Longitudinal portions of the strip having a same length are covered with sacrificial gates made of an insulating material and spaced apart from each other. Non-covered portions of the strip are doped to form source/drain regions. An insulating layer followed by a layer of a temporary material is then deposited. Certain ones of the sacrificial gates are left in place. Certain other ones of the sacrificial gates are replaced by a metal gate structure. The temporary material is then replaced with a conductive material to form contacts to the source/drain regions.Type: ApplicationFiled: September 25, 2019Publication date: January 16, 2020Applicant: STMicroelectronics (Crolles 2) SASInventor: Loic GABEN
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Patent number: 10535695Abstract: Described herein is an electronic device that includes a first integrated circuit die having formed therein at least one photodiode and readout circuitry to convert charge generated by the at least one photodiode to a read voltage and to selectively output the read voltage. A second integrated circuit die is in a stacked arrangement with the first integrated circuit die and has formed therein storage circuitry to selectively transfer the read voltage to at least one storage capacitor for storage as a stored voltage and to selectively transfer the stored voltage to an output. The at least one storage capacitor is formed from a capacitive deep trench isolation. There is an interconnect between the first and second integrated circuit dies for coupling the readout circuitry to the storage circuitry.Type: GrantFiled: March 13, 2018Date of Patent: January 14, 2020Assignee: STMicroelectronics (Research & Development) LimitedInventor: Jeffrey M. Raynor
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Patent number: 10532922Abstract: A micro-electro-mechanical actuator device includes a fixed structure and a mobile structure. The mobile structure includes a first deformable band, a second deformable band, and a third deformable band, both of which extend on opposite sides of the first deformable band, each of which carries a piezoelectric actuator. In a working condition, in which the second and third piezoelectrics are biased, the second and third deformable bands are subjected to a negative bending, while the first deformable band is subjected to a positive bending. There are thus generated two translations that add together, causing a displacement of the first deformable band greater than the one that may be obtained by a single membrane of an equal base area.Type: GrantFiled: November 21, 2018Date of Patent: January 14, 2020Assignee: STMicroelectronics S.r.l.Inventors: Domenico Giusti, Carlo Luigi Prelini
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Patent number: 10534388Abstract: A driver circuit includes a temperature sensor generating a first voltage representative of current operating temperature. An amplifier compares the first voltage to a second voltage representative of an upper threshold operating temperature, and generates a control signal based thereupon. A variable current source generates a load current from the control signal. The amplifier generates the control signal to cause the variable current source to generate the load current as having a magnitude equal to an upper threshold when the first voltage is less than the second voltage. The amplifier generates the control signal to cause the variable current source to generate the load current as having a magnitude that is decreasing until the first and second voltages are equal, and then generates the control signal to cause the variable current source to maintain the load current magnitude at a level at which the first and second voltages are equal.Type: GrantFiled: March 22, 2019Date of Patent: January 14, 2020Assignee: STMicroelectronics S.r.l.Inventor: Santo Ilardo
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Patent number: 10534389Abstract: In some embodiments, a Miller compensation and stabilization device for a feedback control loop includes a capacitor and a control circuit. The capacitor has a first terminal configured to be coupled to an output of a comparator of the feedback control loop and a second terminal. The control circuit is coupled to the second terminal of the capacitor and is configured to control, in response to a voltage applied to a setpoint input of the feedback control loop, a first voltage across the first and second terminals of the capacitor by controlling a value of a potential of the second terminal of the capacitor such that the first voltage is lower than a threshold.Type: GrantFiled: September 13, 2018Date of Patent: January 14, 2020Assignee: STMicroelectronics (Alps) SASInventor: Kuno Lenz
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Patent number: 10534489Abstract: A capacitive discharge circuit includes a line having a capacitance, a switched capacitor circuit including a capacitor, a switched circuit coupled to the line, and a voltage regulator coupled between the switched capacitor circuit and the switched circuit. A controller operates the switched capacitor circuit and switched circuit to in a first phase, charge the capacitor by coupling the capacitor between a common mode and a power supply, and in a second phase, discharge the capacitor by coupling the voltage regulator in series with the capacitor between the power supply node a ground. The controller is also configured to in a third phase, charge the capacitor by coupling the capacitor between the common mode and the power supply, and in a fourth phase, share charge between the line and the capacitor by coupling the voltage regulator and the capacitor in series between the line and the ground.Type: GrantFiled: December 12, 2017Date of Patent: January 14, 2020Assignee: STMicroelectronics Asia Pacific Pte LtdInventors: Chee Weng Cheong, Dianbo Guo, Kien Beng Tan, Yannick Guedon